奈米積體電路銅金屬連線之應力遷移與低介電係數介電層材料時變崩潰的探討

隨著半導體積體電路的持續微縮以及製程技術的不斷演進，由金屬連線本身的電阻與金屬連線之間的介電層在元件微縮化時所衍生的的電阻-電容延遲變成了一個必須面對的難題。為了改善並提昇半導體整合元件的操作速度，銅連線製程與低介電係數介電層材料被引入半導體製程中來降低導線電阻並減低寄生電容效應。然而，銅金屬連線的應力遷移現象與低介電係數材料本身在施加外在電場情形下的時變介電層崩潰效應變成了嚴重的可靠性問題。在本篇研究論文中，針對銅金屬連線的應力遷移問題，藉由有限元素分析法的輔助，模擬了不同的銅連線與低介電係數材料結構的組合來研究其相對應的銅金屬應力遷移現象，同時並分析在有與無輔助銅連接孔情況下的銅應力改善情形。再者，針對一種新的並且特別發生於寬銅線與窄銅線連接結構的銅連線熱金屬遷移現象，除了進行其故障率相對於敏感結構尺寸的相關性研究之外，亦開發了考慮銅缺陷遷移路徑、銅應力分布梯度與銅金屬結構尺寸因素的有限元素分析模擬計算模型來估計應力遷移現象所可能造成的故障率。另一方面，亦依據觀察到的銅缺陷遷移及故障現象，提出了一套當銅缺陷移動時的導線電阻的模擬預估方法，並模擬在不同寬銅線尺寸與窄銅線連接結構銅金屬連線上的應力遷移引起的電阻變化情形。最後，在低介電係數材料的時變介電層崩潰問題的研究方面，針對了在先進元件製程上應用的緊緻與多孔性的氧化矽碳低介電係數材料進行了相關的漏電流、蕭基發射與普爾-法蘭克發射機制的分析。並驗證了在不同電場下的時變介電層崩潰使用時限與電場的平方根的相關性以及此兩種氧化矽碳低介電係數材料的時變介電層崩潰使用時限與故障原因、熱活化能、測試結構長度的關係。本論文除了將銅金屬連線相關的的熱應力遷移問題做更深入的探討，亦提出新的故障模擬、故障率預估與電阻變化預估方法。另外探討了氧化矽碳低介電係數材料的時變介電層漏電與崩潰現象，並對現有的使用時限預估方法提出修正建議。這些結果將有助於更精確並有效地評估半導體銅金屬連線與低介電係數材料的製程可靠度。

關鍵字

應力遷移；時變崩潰；銅金屬連線；低介電係數材料；可靠性

並列摘要

As the dimension of integrated circuits and semiconductor technology continues shrinking, the resistance-capacitance delay induced by metal line and inter-metal dielectrics has become a critical issue. To improve the circuit operation speed, copper interconnects and low-k dielectrics materials are introduced to reduce metal wiring resistance and parasitic capacitance. However, copper stress migration (SM or stress-induce voiding (SIV)) and time-dependent dielectrics breakdown (TDDB) of low-k dielectrics become significant reliability concerns. In this work, Cu SM in terms of different Cu/low-k microstructure scenarios are modeled to understand the voiding evolution with the assistance of finite element analysis (FEA) and explore their dependence with SM susceptibility. Microstructure effects with and without redundant via are also simulated to evaluate their impacts on improving SIV immunity. For a new SM failure mode occurred at narrow metal finger connected with wide lead, failure rate and its geometric dependency are also studied. A computing model considering migration path and hydrostatic stress gradient is used to study the vacancy migration tendency and the influence from effective volume in different geometric scenarios. Another FEA model is also established to simulate the resistance change in terms of void location, void morphology and interconnect scenarios. Regarding low-k dielectrics TDDB, temperature-dependent leakage, Schottky emission and Poole-Frenkel emission of dense and porous low-k SiCO dielectrics are respectively analyzed. TDDB study in low electrical field verifies a square root of electrical field behaviour for low-k SiCO lifetime prediction. Additionally, TDDB with regard to lifetime, failure mechanism, thermal activation energy and length scaling effect are also investigated. As a result, Cu SM and low-k SiCO dielectrics TDDB are characterized for the reference of improvement and risk assessment in advanced semiconductor process.

並列關鍵字

Stress migration ； time-dependent dielectrics breakdown ； Cu interconnect ； low-k dielectrics material ； Reliability

參考文獻

Chapter 1

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[1.4] A. von Glasow, A. H. Fischer, M. Hierlemann, S. Penka, and F. Ungar, “Geometrical aspects of stress-induced voiding in copper interconnects”, in Proc. Advanced Metallization Conf. (AMC), 2002, pp. 161–167.

[1.5] M. A. Korhonen, P. Borgesen, K. N. Tu, and C.Y. Li, “Stress evolution due to electromigration in confined metal lines”, J. Appl. Phys., vol. 73, 1993, pp. 3790–3799.

[1.6] I. S. Yeo, S. G. H. Anderson, P. S. Ho, and C. K. Hu, “Characteristics of thermal stresses in Al(Cu) fine lines. II. Passivated line structures”, J. Appl. Phys., vol. 78, no. 2, 1995, pp. 953–961.

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奈米積體電路銅金屬連線之應力遷移與低介電係數介電層材料時變崩潰的探討

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