應用於電阻式隨機存取記憶體具動態臨界點差異採樣架構之小偏移電流感測放大器

近年來，物聯網的急速發展使高容量、高速與低成本的非揮發性記憶體需求日益增加高並應用極廣。其中，快閃記憶體(NAND Flash Memory)因為提供了低成本與高容量的儲存空間，成了非揮發性記憶體中的主流。然而，快閃記憶體寫入速度慢且無法隨機存取，甚者，快閃記憶體在製成微縮時遇到了瓶頸，因此有其必要開發下世代的非揮發興記憶體。而電阻式記憶體(ReRAM)是相當具有潛力的非揮發性記憶體，其特色為低寫入功耗、小面積、以及具有邏輯製成相容性，可降低製作成本。一個電晶體和一個ReRAM的組合(1T1R)，適合用在需要快速讀取和低供給電壓的內嵌式裝置應用上，特別是電池供給的物聯網裝置。隨著元件的微縮，ReRAM的阻值愈來愈高，且寫入時間和阻值的飄移量愈來愈大，造成高阻態和低阻態之間的R-ratio(RH/RL)縮小。因此ReRAM記憶體在讀取時會面臨到下列問題 1.R-Ratio變小以及製成飄移現象，使得讀取的感測範圍 (sensing margin)變小 2.R-Ratio變小進而造成讀取速度慢在此，我們提出具動態臨界點差異採樣架構之小偏移電流感測放大器 (DTPMS-CSA)。我們提出的DTPMS-CSA的偏差比傳統讀取電路小4.8倍以上。更者，DTPMS-CSA的讀取速度可比傳統讀取電路快1.6倍以上以及3.1倍以上的讀取良率。我們以65奈米製程實作Mb ReRAM記憶體晶片，在正常操作電壓1V以及位元線(Bitline)長度為512個與1024時，量測讀取速度分別為2.6ns和3.14ns。

關鍵字

小偏移電流感測放大器；動態臨界點差異採樣架構；電阻式隨機存取記憶體

並列摘要

In recent years, the growth of IoE devices requires non-volatile memory (NVM) for its large capacity, high speed, low energy and low cost. Flash memory has already been the mainstream of NVM since last century. However, flash memory doesn’t operate fast enough and cannot be accessed randomly. Furthermore, as technology proceeding, flash memory faces difficulties of scaling down to nanometer scale. Necessarily, researchers starts to seek candidates for replacing flash memory. Among all of the inventions, 1T1R ReRAM seems to be a promising choice due to its low write energy, fast speed and logic-process compatibility. 1T1R ReRAM cell is suitable for high speed and low supply voltage embedded applications, particularly for IoE devices with batteries. As size of ReRAM shrinking, cell resistance (RCELL) of ReRAM becomes higher and the wide write time distribution and RCELL reduces the R-Ratio (RH/RL) between high-RCELL state (HRS, RHRS) and low-RCELL state (LRS, RLRS). Thus, ReRAM memory macro suffers the following problem during read : 1.Small read sensing margin (ISM) due to small R-Ratio and process variation 2.Long access time (TCD) due to small R-Ratio Here, we propose Dynamic Trip-Point-Mismatch Sampling Current Sense Amplifier (DTPMS-CSA) to solve the reading problem. DTPMS-CSA achieves 4.8x~7.1x smaller IOS than conventional Current-Latch CSA (CL-CSA). In addition, DTPMS-CSA achieves at least 1.6x faster speed and 3.1x better yield than the conventional one. We implement our proposed SA at a 2Mb 65nm ReRAM macro. At typical VDD and BL-Length=512, DTPMS-CSA achieved 2.6ns read access time. Even more, DTPMS is 1.19ns faster than that of conventional CL-CSA.

並列關鍵字

Small Offset Current Sense Amplifier ； Dynamic Trip-Point-Mismatch Sampling Scheme ； Resistive Random Access Memories

參考文獻

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應用於電阻式隨機存取記憶體具動態臨界點差異採樣架構之小偏移電流感測放大器

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