能帶工程和氮分佈應用在電荷陷阱式快閃記憶體元件

Applications of Band Engineering and Nitrogen Profiles in Charge-Trapping Flash Memory Devices

葉宗浩(Zong-Hao Ye)

指導教授 ： 張廖貴術

國立清華大學/原子科學院/工程與系統科學系/博士(2015年)

https://doi.org/10.6843/NTHU.2015.00516

摘要

隨著個人相機，筆記型電腦和智慧型手機需求的增加，非揮發性記憶體(NVM)技術發展的非常迅速。對非揮發性記憶體元件而言，快速寫入和抹除的特性、優秀的電荷保持力和耐久力是必須的。為了達到這個目標，許多的技術被應用於電荷儲存式快閃記憶體元件上。
在本篇論文中，一開始是回顧快閃記憶體的文獻。 根據文獻的記載，藉由把高介電係數材料應用到電荷儲存式快閃記憶體元件上來改善其寫入和抹除的速度。然而由於高介電係數材料具有較低的結晶溫度，這個特性將導致應用高介電係數材料於電荷儲存式快閃記憶體元件上時會有電荷保持力的問題。為了解決這個問題，氮化矽和高介電係數材料組成的堆疊結構被提出。 實驗結果顯示藉由氮化矽和氧化鉿堆疊形成的儲存層結構能夠改善電荷儲存式快閃記憶體元件的抹除速度和電荷保持力。抹除速度的改善是由於氮化矽的價電帶和矽的價電帶之間的能量差距較小。電荷保持力的改善則是因為對於儲存在氧化鉿的電子要逃脫到氮化矽需要克服一個較大的能帶障礙。此外，電荷儲存式快閃記憶體元件的寫入速度和電荷保持力能夠利用氮化矽/氧化鋁/氧化鉿堆疊結構當作儲存層來進一步地改善。元件的寫入速度被改善是因為許多的注入電荷會被儲存在氮化矽和氧化鋁的介面。元件的電荷保持力被提升則是由於氧化鋁提供了一個較高的能障給從氧化鉿逃脫的電子。
另一方面，為了改善電荷儲存式快閃記憶體的特性，將能帶工程應用於阻擋層是必須的。在這篇論文中各種具有不同能帶結構的堆疊式阻擋層被研究。實驗結果顯示具有高品質二氧化矽(SL)和氧化鋁堆疊形成之阻擋層的元件會有優秀的電荷保持力，而且這個改善並不會犧牲元件的寫入和抹除速度。除此之外，電荷儲存式快閃記憶體元件的寫入、抹除和電荷保持力特性可以藉由氧化鋁/氧化鉿鋁/氧化鋁堆疊形成具有高-低-高(HLH)三層能障結構的阻擋層進一步地提升。並且藉由模擬金屬-絕緣體-金屬(MIM)元件的閘極電流密度來研究具有三層能障結構阻擋層的厚度效應。模擬結果顯示在整體等效氧化層厚度不變的前提下，對於具有HLH能障結構的三層阻擋層，其第二層的厚度薄一點是比較好的設計，因為可以導致較小的閘極電流密度。
最後，在電荷儲存式快閃記憶體元件的閘極介電層中具有不同地氮分佈，其元件的操作特性被研究。對於利用電漿離子佈植(PIII)的方式形成的氮分佈，其氮濃度的峰值會出現在兩個不同的位置。其中比較淺的峰值位於元件的阻擋層，而比較深的峰值則位於元件的儲存層。氮元素具有能夠鈍化界面的缺陷以及增加薄膜中深層能階缺陷的濃度的特性，而這些性質和其在閘極介電層中的位置有關。實驗結果顯示氮元素在閘極介電層中的位置是比其濃度來得重要。另外，我們也總結出對於利用電漿離子佈植的方式將氮摻入電荷儲存式快閃記憶體元件的閘極介電層中，在儲存層靠近穿隧層的地方具有較高的氮濃度並且在阻擋層中具有一個低於18% 的氮濃度是一個最理想的結果。

關鍵字

儲存層 ； 能帶工程 ； 快閃記憶體 ； 模擬 ； 氮化 ； 堆疊

並列摘要

As the demands for personal cameras, laptops, and smart-phones increase, development of nonvolatile memory (NVM) is rapidly expanding. NVM devices with faster programming/erasing (P/E), excellent retention and endurance characteristics are required. To achieve this goal, many methods have been applied to Charge-trapping (CT) flash memory devices.
This dissertation firstly reviews the literature on CT-flash memory. According to the literature, P/E speeds can be improved by applying high-k materials to the charge-trapping layer of CT-flash memory devices. However, its poor retention that arises from the low crystalline temperature of high-k materials is an issue. To overcome this issue, a stacked structure of Si3N4 and high-k materials is proposed herein. Experimental results indicate that a stacked Si3N4/HfO2 charge-trapping layer can improve the erasing and retention operations of CT-flash devices. These improvements are attributed to the smaller valence band offset of Si3N4 to Si and the higher barrier for electron detrapping from HfO2 to Si3N4. The programming and retention characteristics of CT-flash memory devices can be further enhanced by a Si3N4/Al2O3/HfO2 as the CT layer to increase the number of injected charges that are trapped at the Si3N4/Al2O3 interface, and to provide a high barrier to electron detrapping from HfO2.
Band engineering must be performed on the blocking layer to improve the performance of CT-flash memory. In this dissertation, various stacked blocking layers with various band structures are studied. The results indicate excellent data retention of devices with a sealing layer (SL) / Al2O3 blocking layer without loss of P/E speeds. The programming, erasing, and retention characteristics of CT-flash devices can be further enhanced by using the high/low/high (HLH) triple barrier structure with Al2O3/HfAlO/Al2O3 blocking layers. The effects of thickness of the blocking oxides in a multilayer barrier structure are studied by simulating the gate current density in a metal/insulator/metal (MIM) device. All MIM structures with triple insulator have the same electrical oxide thickness (EOT) and different thicknesses for each layer. Simulation results show a thin second layer for triple blocking layer with an HLH barrier structure is preferred because its gate current density is smaller.
Finally, the operating characteristics of CT-flash devices with different nitrogen profiles in gate stack are studied. Two peaks in the nitrogen depth profile are formed by plasma immersion ion implantation (PIII) nitridation treatment. A shallow peak is obtained in the blocking layer and a deep peak is obtained in the CT layer. Nitrogen can passivate defects in the interface and increase the number of deep trapping sites in the bulk. Therefore, the properties of nitrogen are determined by their locations in the gate stack. The results indicate that the nitrogen profile in the gate stack is more important than the nitrogen concentration therein. A nitrogen profile that has a deep peak with a high concentration and shallow one with a suitable concentration (< 18 %) is optimal for PIII nitridation treatment.

並列關鍵字

charge-trapping ； band engineering ； flash memory ； simulation ； nitridation ； stacked

參考文獻

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