近年來,高傳輸速率與傳輸質量受到高度重視。雖然多輸入多輸出(MIMO)系統能夠滿足以上兩項要求,但多天線傳輸造成的大量能源消耗被認為是新的問題。因此,研究學者們提出多輸入多輸出空間調變技術(GSM-MIMO),通過減少發射天線數量(active antenna)降低能源消耗,並使用天線的空間多樣性增加傳輸速率。本論文提出的演算法是基於CECML-OB-MMSE的硬體設計,稱為共享索引運算於CECML的低複雜度64x4空間調變多輸出多輸入偵測器。在天線索引選擇時,提出的演算法使用共享索引方法取代記憶體存取,以減少計算複雜度和記憶體的硬體資源。此外,我們使用並行技術調整硬體執行時間與面積之間的平衡。在符號偵測部分,我們使用Joint QR-SIC偵測器取代MMSE偵測器,以避免反矩陣運算。最後,我們在提出的演算法中加入錯誤更正碼,使其BER效能接近ML。新演算法的硬體設計通過FPGA驗證,且在本論文中有硬體面積、時間與能量的分析。
The high data rate and the quality of transmission is attached great importance in recent years.Though the multiple-input-multiple-output (MIMO) system can achieve these requirement, the new MIMO technology called generalized spatial modulation MIMO (GSM-MIMO) that has additional consideration about power consumption.This thesis proposes a hardware design of CECML-OB-MMSE detector cite{CECML} called parallel 4 shared index processing with joint QR-SIC in GSM-MIMO system.At the index selection, the new algorithm uses shared index method instead of memory access to reduce hardware resource and computational complexity.And the parallel technology trades off the hardware latency and area. At the symbol detection, we use joint QR-SIC detector cite{JQRSIC} instead of MMSE detector to avoid matrix inverse and decrease hardware latency.After using error correction code (ECC), the BER performance of this algorithm is close to maximum likelihood (ML).The hardware architecture is designed and verified by FPGA and TSMC90nm.The analysis of hardware area, hardware timing and hardware power are presented as well.