提升記憶體錯誤辨別率與良率之記憶體測試資料分析方法

Failure-Pattern-Based Memory Test Data Analysis for Failure Classification and Yield Improvement

林斌彥(Bing-Yang Lin)

指導教授 ： 吳誠文

國立清華大學/電機資訊學院/電機工程學系/博士(2015年)

摘要

能夠順利畢業，我第一個想感謝的是吳誠文老師。我在實驗室裡做的每項研究，老師都很有耐心地一遍又一遍指導我不足的地方，包括對事情的思考、判斷方式以及技術上的觀念等等。除了研究，在表達和待人接物上我也從老師身上學到許多。每次開會時，老師的指導都讓我感覺醍醐灌頂，也每次都讓我意識到還有很大的空間需要學習以及加強。在投稿論文的時候，老師雖然行程十分忙碌，卻仍然排開空檔、犧牲假日時間，一字一句、不厭其煩地幫忙更正語意以及內容，甚至因為截稿時間的關係，在晚餐時間餓著肚子、幫忙修改論文到最後一刻，此舉讓學生真的非常感動。老師待人溫厚，對學生的關懷都像對自己家人一樣，讓我見識到像老師這樣有成就的人，處事的出發點時時刻刻都是為了關懷、為了別人。
我第二個想感謝的人是李旻昇學長，在我剛進實驗室的時候，李旻昇學長的租屋處離學校很近，我常常和學長一起吃飯，討論研究和未來的打算。這樣的頻繁討論使我對專業知識有困惑時，都能在第一時間找的到專家詢問。每次在研究上有所進展時，學長總是不吝於給予鼓勵，讓我充滿信心、並對研究充滿興趣。另外，我想感謝和我同屆的周盈妏和吳姿欣在修課以及生活上給予的鼓勵及幫助。雖然已經過了好幾年，我仍然時時懷念起我們一起籌備活動、一起出遊的那些歡樂時光。我也想感謝台積電合作計畫的夥伴們。在我的碩博士生涯裡，台積電的夥伴們提供了許多寶貴的資料以及真實待解的問題，讓我們得以發揮、並試圖解決業界所面臨的真實問題，這個機會真的十分難得，讓我分外珍惜。
我特別想感謝的是讓我無後顧之憂、得以專心完成學業且疼愛我的爸媽，兩位姊姊，祖父母、外公外婆、舅舅，以及其他家人們。是家人們的支持，我才一直有信心和信念、完成學位。在接下來的日子裡，我將懷著感恩的心情，繼續與家人一起分擔、分憂、分享生活的大小事。最後，感謝我周遭所有的朋友們，是你們的鼓勵以及包容，才讓我得以順利完成論文，謝謝你們。

關鍵字

記憶體診斷 ； 修復架構分析 ； 自我修復電路 ； 系統單晶片 ； 良率提升 ； 測試資料壓縮 ； 測試資料分析 ； 記憶體測試 ； 錯誤位圖 ； 修復架構分析 ； 備用記憶體修復 ； 三維記憶體 ； 自我測試電路 ； 錯誤分析 ； 錯誤樣型識別

並列摘要

Memories have been considered as one of the major drivers of CMOS technology, due to their high density, high capacity, critical timing, sensitivity, etc. Memory diagnosis is therefore important for technology and product development. In memory diagnosis, memory test data need to be collected and analyzed. However, as memory density and capacity continue to grow, the amount of test data also keeps increasing, making it difficult to extract useful information for further diagnosis and analysis. In this thesis, we propose a test data compression technique, which compresses the fail bitmaps into different failure formats, resulting in more compact storage and faster access in the future. Experimental results show that for memories with different failure distributions, the failure bitmaps can be compressed to 21.03-57.26% of their original size without information loss.
For memory diagnosis, memory failure pattern identification is traditionally considered as a key task to speed up the memory diagnosis and failure analysis process. A memory failure pattern is defined as a topological distribution of fail bits in the memory array. The critical memory failure patterns (those are found frequently, so are the yield killers), however, may change in different memory designs and process technologies. It is difficult to consider all critical failure patterns beforehand as they are not be defined in advance. To solve this problem, we propose a memory failure pattern identification system, which can identify critical memory failure patterns from a large amount of memory failure bitmaps automatically, even if they are not defined in advance. In our experiment for 132,488 4-Mb memory failure bitmaps, the proposed failure pattern identification system can automatically identify 6 critical yet undefined failure patterns in minutes, in addition to all known patterns. In comparison, the state-of-the-art commercial tools need manual inspection of the memory failure bitmaps to identify the same failure patterns.
Another approach to improve the memory yield is redundancy repair, which uses redundancy to repair (replace) faulty parts of memories. To ensure high repair efficiency and final product yield, it is necessary to explore and develop memory redundancy architectures carefully. However, due to different memory failure distributions and design constraints of memory architectures, it is difficult to explore the efficiency of different redundancy architectures thoroughly. To solve this problem, we propose Raisin-C, which can be used to simulate the repair rates of different memory redundancy architectures with 2D and 3D redundancy constraints. In our experiments, the repair rates of 10 different 3D redundancy architectures with 3 different redundancy analysis algorithms in a given failure pattern distribution are simulated. The experimental result shows that the difference of the repair rates between the most efficient and least efficient memory redundancy architectures is up to 49.42%.
In addition, to improve the stack yield of channel-based 3D DRAM, in this thesis, we introduce two redundancy schemes, i.e., Cubical Redundancy Architecture 1 and 2 (CRA1 and CRA2) [1], and propose two 3D redundancy schemes, i.e., Configurable Cubical Redundancy Architecture 1 and 2 (CoCRA1 and CoCRA2). The difference between CRAs and CoCRAs is that the spare memory of CoCRAs is configurable to allow efficient repair of row, column, and cluster failures, while that of CRAs only has one type of spare configuration. In (Co)CRA1, the global spares that can be shared across dies are associated with each DRAM die as conventional DRAMs. In (Co)CRA2, we use an SRAM on the logic die as global spares, which have higher flexibility than CoCRA1. The experimental result shows that CoCRA1 can achieve 28.09% higher stack yield than the traditional redundancy architecture, with only 50% of its spare space. There is only 0.05% and 0.2% area overhead on the logic die and DRAM die, respectively. On the other hand, CoCRA2 can further improve the stack yield to almost 100%, but with 2.3 times higher area overhead than CoCRA1.

並列關鍵字

memory diagnosis ； redundancy analysis ； memory builtin- self-repair (BISR) ； SOC ； yield improvement ； test data compression ； test data analysis ； memory testing ； memory diagnosis ； fail bitmap ； redundancy analysis (RA) ； redundancy repair ； 3D RAM ； memory testing ； failure analysis ； failure pattern identification ； failure bitmap

參考文獻

[1] W.-T. Chiang and C.-W. Wu, "3D Redundancy Architecture for Wide-I/O DRAM," Master Thesis, Dept. Electr. Eng., National Tsing Hua University, 2012.

[4] B.-Y. Lin, M. Lee, C.-W. Wu, "A memory failure pattern analyzer for memory diagnosis and repair," in Proc. IEEE VLSI Test Symp. (VTS), pp. 234–239, Apr. 2012.

[7] A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice. Chichester, England: John Wiley & Sons, 1991.

[9] V. N. Yarmolik, S. Hellebrand, and H. Wunderlich, “Self-adjusting output data compression: An efficient BIST technique for RAMs,” in Proc. Conf. Des., Aut., Test Eur. (DATE), pp. 173–179, Feb. 1998.

[11] S. Hellebrand, H. Wunderlich, A. Ivaniuk, Y. Klimets, and V. N. Yarmolik, “Efficient online and offline testing of embedded DRAMs,” IEEE Trans. Comp., vol. 51, no. 7, pp. 801–809, Jul. 2002.