高速及高擺幅光通訊調變器驅動電路設計

Design of High Speed and High Swing Modulator Drivers for Optical Communications

林執正(Chih-Cheng Lin)

指導教授 ： 徐碩鴻

國立清華大學/電機資訊學院/電子工程研究所/碩士(2018年)

摘要

隨著資料傳輸與處理量日益增加，為了解決傳統金屬導線所造成的非理想效應，越來越多研究著手在光連結系統上。在此篇論文中，我們著重在設計超高速光通訊的前端驅動電路，希望能設計出傳遞40Gb/s訊號速度且達到輸出4伏特擺幅的調變驅動電路。第一章針對調變驅動電路的背景及設計難度作介紹，第二章則是統整了現今常用的各種寬頻技巧做深入的分析及介紹，第三章到第五章則是就實際下線的模擬及量測結果討論架構特性，第六章是就與工研院合作計劃中做的電路來介紹，最後在第七章作出結論。
第三章是運用傳統的調變驅動電路架構搭配低臨界電壓的電晶體實作於40 nm CMOS製程，由於臨界電壓需求較小相較於一般的RF MOS可利用較小的尺寸達到相同的放大倍率，因此藉由縮小寄生電容來放大頻寬，此電路中的電感皆是使用三維螺旋形電感，所以有極小的晶片面積0.620.53 〖mm〗^2。
第四章提出了為改善傳統電阻式負回授架構限制頻寬的問題，新設計的聯級擺幅補償架構的40 Gb/s調變器驅動電路，實作於90 nm CMOS 製程中，此架構雖然能夠達到較大的頻寬，但供應電壓必須設計在3.4/6.5V的情形下此電路消耗功率會提高到916 mW，而晶片面積0.870.97 〖mm〗^2。。
第五章則是進一步改良所提出的聯級擺幅補償架構電感peaking的方式，並增加了前級的pre-peaking stage，因此而能在維持輸出4〖.5V〗_PP的情況下進一步的增加頻寬，並且降低供應電壓致3.4/6 V，使得功耗降低至約為767.2mW。
第六章藉由與工研院合作的計畫嘗試了不同於一般的電路架構及製程做設計，分別是使用65 nm CMOS分散式放大器電路架構和130 nm SiGe HBT元件做設計，就模擬結果能達到更好的頻寬及輸出擺幅表現。最後在第七章作出結論及規格比較表。

關鍵字

調變器驅動電路 ； 光連結系統

並列摘要

With the rapidly increased demand of data rate for signal transmission, many researches put significant efforts on optical interconnects to solve the issues of speed limitation in conventional metal lines. In this thesis, we focus on designing ultra-high speed front-end circuits of optical communications to achieve a 40Gb/s modulator driver with 4V_PP output swing. The first chapter shows the challenges and background of modulator driver design. The second chapter lists the common broadband techniques and some detailed analysis. The third to fifth chapters show the simulation and measurement results of the circuits. The sixth chapter introduces two circuits with ITRI’s project. And a conclusion is given in chapter seven.
In chapter 3, a low-Vt MOS is employed in a conventional topology of modulator driver in 40 nm CMOS. Due to the lower voltage requirement, those low-Vt MOS transistors can achieve the same gain but with smaller sizes, and further broaden the bandwidth. The chip area is 0.620.63 μm2 including two 3D solenoid inductors.
In chapter 4, a new circuit topology is proposed based on cascade swing compensation to alleviate the bandwidth limitation from the conventional topology. The circuit is realized in 90 nm CMOS process. With the relatively large supply voltage of 3.4/6.5 V, the power consumption increased to 916 mW with a chip area of 0.870.97 m2.
In chapter 5, a further modified broadband technique with cascade swing compensation topology is designed. Based on measurement results, a 4.5 V_PP output swing is achieved with a 767.2 mW power consumption, and the chip area is 0.870.97 〖μm〗^2.
In chapter 6, two different types of modulator drivers were proposed due to the cooperation project with ITRI. The first circuit topology is distributed amplifier (DA) which is fabricated in 65 nm CMOS process. With the series of inductors between each stages all parasitic capacitances can be merged as a transmission line connections. That reduces input and output poles, then broaden bandwidth. The other circuit was fabricated with 130 nm SiGe HBT from IHP. By using the advantages of high f_T and high breakdown voltage characteristics of the device, the circuit can obtain a much better performance with high speed and high output swing. But a series of buffer stages are necessary to prevent the leakage current from base node during large signal transmission.
And the final conclusion and specification comparison table with the presented papers are introduced in chapter 7.

並列關鍵字

Modulator driver ； Optical interconnect system

參考文獻

REFERENCES

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