電荷缺陷儲存式快閃記憶體側向位移之模型分析

Analysis and Modeling of Lateral Migration for Charge Trapping Flash Memory

古依純(I-Chun Ku)

指導教授 ： 連振炘 ； 施君興

國立清華大學/電機資訊學院/電子工程研究所/碩士(2010年)

摘要

近年來，矽-二氧化矽-氮化矽-二氧化矽-矽（SONOS）型記憶體逐漸成為非揮發記憶體中的主流，隨著製程的演進，SONOS型記憶體亦面臨到尺寸微縮後可靠度之問題，在主要的微縮議題，即此儲存於氮化矽層中載子將會出現側向遷移（Lateral Migration）現象，由於操作上所產生的熱擾動及多次循環讀寫/抹除後，造成電荷缺陷儲存式快閃記憶體其儲存載子濃度與分布的改變，進而往通道內部方向不斷延伸，使得臨界電壓發生變異（Threshold Voltage Variations）進而影響記憶體單元的操作。
本文中，提出注入氮化矽缺陷層中的載子在經過時間與電壓的操作下會進行側向的擴散之模型，利用擴散方程式計算載子在擴散後對時間與位置之分布，在加入臨界電壓變異模型，將所儲存的載子對臨界電壓值的貢獻皆歸於平帶電壓中，如此便可以得到在理想情況中，電荷以擴散方式之側向遷移對長通道元件的臨界電壓變異模型。再利用二維元件模擬軟體（MEDICI）來做電性分析，將不同的通道長度中，以量化的方式，對氮化矽中的載子的設定，以達到將固定載子數量放在捕捉層之目的，改變預設之載子濃度與側向擴散之長度，以分析載子分布對元件電性之影響，根據模擬之電性結果與所建立之物理分析模型比較，希望發展及建立側向遷移行為之物理分析模型。

關鍵字

快閃記憶體 ； 缺陷 ； 側向位移

並列摘要

Recently, Flash technology is gradually migrated from floating-gate cells to charge-trapping devices due to lowing operating voltage and two-bit storage. However, it also a great challenge for that the local distributions of trap charges will be lateral migrated after thermal various or endurance operation. Since the gate length of the cell devices are continued to scale down, it is crucial to realize the impacts of lateral migration on device characteristics for the programmed and the erased SONOS cells, specially the variations of threshold voltage.
In this paper, using diffusion equation to realize the retribution of trapped charge, and then developing the model from gate voltage equation to provide a sound understanding of threshold voltage variations due to lateral migration. Through two-dimensional TCAD simulator MEDICI, the trapped charges are distributed uniformly within the nitride layer. And the conservation of the total trapped charges is assumed in this study. The characteristic lateral migration lengths are used to indicate the degree of lateral migration. Compare the results between the simulation and the modeling to analysis what is the reason in the difference. Eventually, we hope to develop a theoretical model to explain the retention loss characteristics by lateral-migrated trapping charges.

並列關鍵字

flash memory ； trap ； lateral migration

參考文獻

[1] Pavan Paolo, Bez Roberto, Olivo Piero and Zononi Enrico,“Flash Memory Cell-An Overview” Proc. IEEE, pp. 1248-1271, 1997.

[3] International Technology Roadmap for Semiconductor, 2007 edition.

[6] K. Prall, “Scaling Non-Volatile Memory Below 30nm,”in Proc. NVSMW, pp. 5-10, 2007.

[8] M. H. White, D. Adams and J. Bu. “On the Go With SONOS,” IEEE Circuits Devices Mag., pp. 22-31, 2000.

[9] C. H. Lee, et al., “A novel SONOS structure of SiO2/SiN/Al2O3 with TaN metal gate for multi-giga bit flash memories,”in IEDM Tech. Dig., 2003, pp.613-616.