嚴謹的設計、模擬與分析高頻VLSI時鐘樹

Rigorous Design, Modeling and Analysis of High-Frequency VLSI Clock Trees

陳畯學(Hsin-Hsieh Chen)

指導教授 ： 張克正

國立清華大學/電機資訊學院/電機工程學系/碩士(2011年)

https://doi.org/10.6843/NTHU.2011.00701

摘要

時脈訊號是同步電路設計中最重要的部份，一個擁有好的時脈訊號的電路才能算是一個好的設計，而clock skew與clock jitter更都是關乎設計能否合乎規格的重要因素之一。

所以大家無不汲汲營營發明各種繞線演算法企圖去降低clock skew或clock jitter，在過去僅考慮電阻與電容的情況下，目前的演算法大致可解決clock skew與clock jitter的問題，但隨著製程地演進與頻率進入GHz的時代，由於電路阻抗Z=R+jωL，ω=2πf，頻率越來越高，感抗的效應變得跟阻抗一樣重要，甚至比阻抗還要大，如果再考慮到串音效應，電感會變得非常重要，尤其是在會常常快速改變訊號的時脈訊號，如果不能準確的把寄生電阻、電容與電感抽取出來並模擬，晶片很可能就會出現訊號判斷錯誤 (false switch)的情形，但現在市售的商業軟體，往往忽略了電感的效應，應該是說他們不知道如何分析電感，所以假裝看不見電感，如此一來很可能造成clock skew誤判的情形，晶片良率下降，不確定性增加。有鑑於此，我們研究開發了一全新的軟體: ClockHenry，以方便時鐘樹設計者抽取SPICE netlist中的寄生電阻、電容與電感值。

此外我們研究主張採用一種新穎的時鐘樹繞線策略：時鐘樹遮罩繞線 (clock shield routing)最佳化現有的時鐘樹環境以期能夠達到降低加入電感考量造成clock skew變大的情況。本篇論文我們會列舉五個不同floorplan架構的SoC設計為基礎，並分別採用多種不同風格的時鐘樹繞線方式，block level採用一般APR軟體提供的傳統非對稱時鐘樹繞線方式，而global clock採用full-custom 對稱的H-tree或清大蔡仁松教授的exact zero skew時脈繞線演算法，分別量化分析傳統時鐘樹繞線和時鐘樹遮罩繞線有無加入電感考量的電性表現。

然而不幸地製程的參數會因為一些不確定因素，像環境變化、儀器的不同......等而有所變動，所以如何快速有效率的分析與模擬不可避免的製程變動也非常重要。由公開的文獻[12]可知，製程變動主要分為三類，分別為device、system、interconnect製程變動，而我們主要研究的目標在interconnect與system的製程變動，主要變動的參數像是線寬 (metal width)、線厚 (metal thickness)、層間介電層厚度 (interlayer dielectric thickness, ILD thickness )與power supply voltage，本篇論文最後也會利用我們的時序分析方法量化不同的時鐘樹繞線風格在interconnect與system製程變動下的電性表現並證明與傳統時鐘數繞線相比時鐘樹遮罩繞線較不敏感於製程變動。

然而時鐘樹遮罩繞線並非完美無缺的，它也伴隨一些缺點，其中最重要的是面積與平均時脈功耗的補償，本篇論文我們也會針對幾種代表性的時鐘樹遮罩繞線方法，量化分析其面積與平均時脈功耗，提供時鐘樹設計者在設計時脈時的取捨標準。

最後，我們比較採用我們的SoC繞線方法與Astro的SoC繞線方法關於clock skew的成果，這邊我需要特別強調的是我們觀察到CIC提供的Synopsys Astro只能給予設計者晶圓廠提供的電阻與電容表格，因此我們台灣學術界須採用額外的軟體以期加入電感的考量，本實驗室也開發了這樣的軟體取名為ClockHenry，它可幫助設計者有效率地萃取電阻、電容與電感表格取代CIC給予我們的電阻與電容表格以利於整體SoC clock trees的模擬。由於H-tree或exact zero skew時脈繞線演算法設計出發點是假設金屬線的每單位長度的電阻、電容都相同，此概念與遮罩後的時脈線不謀而合，所以採用時鐘樹遮罩繞線後clock skew的改善效果相當不錯。而Astro的時鐘樹繞線演算法是採用加入clock buffers以平衡各時脈路徑的延遲時間，加入clock buffers的數量與位置是根據傳統時鐘樹繞線環境去設計的，所以採用時鐘樹遮罩繞線後clock skew的改善效果不見得會很好。

關鍵字: 同步電路、時脈偏斜、時脈抖動、高頻、部份電感、迴路電感、電感矩陣、晶片電感模擬、時鐘樹遮罩繞線、系統晶片時鐘樹、射頻晶片時鐘樹、H型時鐘樹、絕對零偏斜時脈繞線演算法、時脈緩衝器的添加、預備時間的違反、維持時間的違反、偶 (奇、共)模、平均時脈功耗、互連線的變異、供電壓的變異、面積的補償、新思Astro、分散式模型、量產可行性設計。

關鍵字

同步電路 ； 時脈偏斜 ； 時脈抖動 ； 高頻 ； 部份電感 ； 迴路電感 ； 電感矩陣 ； 晶片電感模擬 ； 時鐘樹遮罩繞線 ； 系統晶片時鐘樹 ； 射頻晶片時鐘樹 ； H型時鐘樹 ； 絕對零偏斜時脈繞線演算法 ； 時脈緩衝器的添加 ； 預備時間的違反 ； 維持時間的違反 ； 偶 (奇、共)模 ； 平均時脈功耗 ； 互連線的變異 ； 供電壓的變異 ； 面積的補償 ； 新思Astro ； 分散式模型 ； 量產可行性設計

並列摘要

Clock signal is the most important part in synchronous circuit and a good circuit design must have a robust clock signal. Clock skew and clock jitter are the most critical factors whether the design meets the specifications or not.

Therefore, many devote to inventing some routing algorithms attempting to reduce the clock skew or clock jitter. In the past, we only considered the effects of resistance and capacitance. Those algorithms can generally solve the clock skew and clock jitter problems. However, with the advance of silicon process and giga-hertz-level frequency, the effect of inductance has become as important as that of resistance, or even greater than the resistance. For crosstalk effect, the inductance becomes very important, especially in the fast-switching signals like clock signals. Furthermore, the chip may catch the wrong signals (false switch) if we cannot extract parasitic resistance, capacitance, inductance and simulate them accurately. But now, the commercial software usually ignores the effect of inductance. It should be said that they do not know how to analyze the inductance, so they pretend that they can’t see the inductance. As a result, it is likely to misjudge the value of clock skew, decrease the chip yield and increase uncertainties. In view of this, we develop novel software: ClockHenry. It’s convenient to extract parasitic resistance, capacitance and inductance in the SPICE netlist for clock tree designers.

Besides, we advocate using a new clock tree routing strategy: clock shield routing for clock nets. The clock nets should be optimized based on EM waves in order to decrease the clock skew due to the effect of inductance. After adopting the clock shield routing approach, there is still need to judge the clock skew by modeling the effect of inductance accurately. In this thesis, I will enumerate five kinds of floorplan architectures and route the clock trees with a variety of comprehensive styles of clock tree routing strategies. We route block-level clock lines with traditional and asymmetric clock tree routing approach and then we route global clock lines with full-custom symmetric H-tree or with exact zero skew clock routing algorithm proposed by NTHU Professor Ren-song Tsay. Then, we analyze quantitatively the electric properties according to our comprehensive sets of clock design ideas.

Furthermore, the process parameters may change due to uncertain factors such as environmental variations, different instruments, etc. So how to analyze and simulate inevitable process variations efficiently and accurately is also very important. We know that process variations can be divided into three categories namely (a) device, (b) system and (c) interconnect process variations from public domain literature [12]. We will focus on interconnect and system process variations. The main variable parameters are metal width, metal thickness, interlayer dielectric thickness (ILD thickness) and power supply voltage. Using interconnect and system process variations, we can quantify the electric properties between different clock tree routing methodologies along with our timing analysis method. In this way, we deomonstrate the clock shield routing strategy is less sensitive to process variations compared with traditional clock routing strategy.

However, the clock shield routing strategy is not perfect since it has some disadvantages. The most important two are silicon area and average clock power dissipation penalties. In this thesis, we describe representative clock shield routing approaches along with the corresponding area and average clock power dissipation penalties, which are in the range of.

Finally, we experiment on the clock skew performance between our SoC clock routing and Astro clock routing approaches. We observe that Synopsys Astro versions from CIC can only give designers the resistance and capacitance tables from the foundries. Therefore, the academia in Taiwan must add the effect of inductance into consideration by extra software, which is implemented in our lab and is called ClockHenry that can extract resistance, capacitance and inductance tables to supersede CIC tables available. We need Clock Henry to facilitate the overall simulation of SoC clock trees. Because the foundations of H-tree or exact zero skew clock routing algorithm are based on the same resistance and capacitance per unit length. And these concepts coincide with clock lines after shielding. So clock skew can be approved after adopting clock shield routing algorithm. However, the foundation of Astro clock routing approach is to balance delay time of each clock path. How to determine the number and location of clock buffers is according to the environment of traditional clock trees. The improvement of clock skew may not be very good after adopting clock shield routing algorithm.

Keywords: synchronous circuits, clock skew, clock jitter, high-frequency, partial inductance, loop inductance, inductance matrix, on-chip inductance modeling, shield, SoC clock tree, RF clock tree, H-tree, exact zero skew clock routing algorithm, clock buffer insertion, setup time violation, hold time violation, even (odd, common) mode, average clock power dissipation, interconnect variation, power supply voltage variation, area penalty, Synopsys Astro, distributed model, DFM.

並列關鍵字

synchronous circuits ； clock skew ； clock jitter ； high-frequency ； partial inductance ； loop inductance ； inductance matrix ； on-chip inductance modeling ； shield ； SoC clock tree ； RF clock tree ； H-tree ； exact zero skew clock routing algorithm ； clock buffer insertion ； setup time violation ； hold time violation ； even (odd, common) mode ； average clock power dissipation ； interconnect variation ； power supply voltage variation ； area penalty ； Synopsys Astro ； distributed model ； DFM

參考文獻

[1] Li-Fu Chang, Keh-Jeng Chang and Robert Mathews, "When Should On-Chip Inductance Modeling Become Necessary for VLSI Timing Analysis," in Proceedings of the IEEE International Interconnect Technology Conference (IITC), 2000, pp. 170-172.

[2] Kenneth L. Shepard and Vinod Narayanan, "Noise in Deep Submicron Digital Design,” in Digest of Technical Papers IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 10-14 Nov. 1996, pp. 524-531.

[8] Eby G. Friedman (Ed.), Clock Distribution Networks in VLSI Circuits and Systems, IEEE Press. 1995.

[12] Payman Zarkesh-Ha, Tony Mule and James D. Meindl, “Characterization and Modeling of Clock Skew with Process Variation,” in Proceedings of IEEE Custom Integrated Circuits Conference (CICC), 1999, pp. 441-444.

[14] Ying Liu, Lawrence T. Pileggi and Andrzej J. Strojwas, “Model Order- Reduction of RC (L) Interconnect including Variational Analysis,” in Proceedings of the 36th Design Automation Conference (DAC), 1999, pp. 201-206.