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  • 學位論文

考慮資源限制下之動態IC設計專案派工架構

A dynamic project dispatching framework with resource constraints in IC design industry

指導教授 : 簡禎富
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摘要


半導體製程隨著摩爾定律的演進,晶圓的複雜度也日益提高。在面臨全球化競爭與產品生命週期縮短的趨勢下,IC設計公司需提供更快速的開發速度來確保其服務品質與競爭力。其中IC設計工程師通常藉由電子設計自動化工具來輔助設計案或模組開發以增加專案開發效率,但是分析系統的效能往往受限於電腦資源的限制。隨著軟體資源與硬體價格日漸昂貴的趨勢,以往藉由直接購買硬體資源來解決系統效能不足的方式已不敷效益。因此透過適當的資源配置來提高系統的整體效能來增加公司的設計產出即為一重要的議題。在本研究所提出的考慮資源限制下之動態IC設計專案派工架構中,藉由定義多項指標將原本抽象的工作與資源概念加以量化,以協助決策者更清楚地了解複雜的系統實務狀況。本研究透過建立標準工時預測模型估計加工時間作為工作優先權的依據,並依損失函數比較多項可行的工作指派規則,針對工作排隊權重與機台使用順序進行相關的探討等步驟以提高系統分析效能,藉由模擬實驗的方式,取得不同情境下之最佳參數設定與派工策略,以提高系統的整體分析效能,進而減少工程師的等待時間同時贈加IC設計的產出,最後以新竹某IC設計服務公司為研究案例以驗證本研究之效度。

關鍵字

IC設計 EDA 資源分配 派工排程 模擬

並列摘要


As the rapid development of technology of semiconductor manufacturing, the IC designs have become increasingly complicated so that IC design processes have relied on heavy computer analysis that requires capital investment for computing resources. However, the computer resource is expensive and limited, and therefore it became a critical problem to well allocate the computer resource. This study aimed to develop a dynamic policy to integrate and arrange the computer resources. Several indicators were defined to quantify the vague workload and service rate, and hence the user can get a good understanding on the situation of system and resource easily. The best one and its parameter setting would also derived from a series of simulation study. Furthermore, five potential assignment policies were compared to validate the proposed approach. The empirical study conducted in IC design service corporation has validated the developed solution.

參考文獻


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