異質多核心功耗模擬器之設計與實驗

The Design and Experiments of A Heterogeneous Multicore Power Simulator

林承諺(Cheng-Yen Lin)

指導教授 ： 李政崑

國立清華大學/電機資訊學院/資訊工程學系/博士(2015年)

摘要

嵌入式多核心系統在現今的消費電子產品設計中扮演著越來越重要的角色，這樣的系統配備著多個異質運算單元，用以滿足現代新興應用的運算需求，此類產品往往是配備著電池的行動裝置，所以在應用開發人員的優化目標上必須同時考量效能以及功耗優化技術。然而，目前廣泛被軟體應用開發人員所使用的SID模擬器開發平台，卻缺少了功耗估算的功能，使得應用開發人員沒辦法利用這平台來開發功耗優化的相關技術。

在本論文中，我們利用了SID模擬器開發工具，開發了一個異質多核心的功耗模擬器，我們的功耗模擬器除了提供全系統的模擬功能之外，亦可以針對系統上模擬的相關硬體IP，進行功耗估算的動作，其中包含了主要運算核心單元、數位訊號處理器、指令快取、記憶體系統、以及相關的周邊。我們的功耗估算流程主要是分為兩階段，分別是IP功耗模型的建立以及系統功耗模擬，在第一階段IP功耗模型的建立中，我們使用了PowerMixer{IP}這套工具，來針對系統上模擬的硬體IP，一一的建立起相對應的功耗模型，這些功耗模型之後被應用於第二階段的系統功耗模擬中，透過我們所提出的方法來分析模擬過程中產生的相關紀錄檔，從中萃取出影響功耗的相關參數，再藉由我們開發的CPE功耗分析模組，而得到最後功耗估算的數據，此外我們也提供了一套功耗分析的函式，讓軟體應用開發人員，可以任意的呼叫使用，針對特定的程式碼進行功耗分析，進而優化其軟體所消耗的功耗。我們的異質多核心功耗模擬器可以同時平行模擬多顆的數位訊號處理器，為了維持一定的模擬效能，我們也開發了一個管理元件，將每個模擬的數位訊號處理器一一對應到模擬主機上的執行緒上來執行，同時此管理元件也會處理數位訊號處理器彼此間共享資源的存取需求以及進行同步的功能。

最後我們也藉由一系列的實驗來展示此異質多核心功耗模擬器的功能，首先我們利用了DSPstone benchmark來討論不同的編譯器優化選項對於數位訊號處理應用軟體的效能與功耗影響，再來我們也評估了一些多核心應用軟體，其中包含了FIR數位濾波器、人臉辨識暨表情誇張化應用以及前車偵測應用，在這過程中我們展示了軟體應用開發人員可藉由我們的功耗模擬器所提供的不同面相功耗評估數據來開發相對應的功耗優化技術。

關鍵字

多核心系統 ； 嵌入式系統 ； 數位訊號處理器 ； 模擬器 ； 功耗優化技術 ； 系統工具軟體

並列摘要

Embedded multicore systems are playing increasingly important roles in the design of consumer electronics.
Such systems may provide heterogeneous computation power to meet the performance demand of modern applications.
As many of the devices are with batteries, the objective of such systems is to optimize both performance and power characteristics of mobile devices.
However, currently there are no power metrics supporting popular application design platforms (such as SID), that application
developers used to develop their applications. This hinders the ability of application developers to optimize power consumption.
In this thesis we present the design and experiments of
a SID-based power-aware simulation framework for heterogeneous multicore systems. The proposed power simulator allows a full system simulation with power
estimation support for targeting the intellectual properties (IP) used
in the platform, including a main processing unit, digital signal processors (DSPs), instruction cache,
memory subsystems, interconnections, and DMA.
Our power estimation flow includes two phases, IP-level
power modeling and power-aware system simulation. The first phase employs
PowerMixer{IP} to construct the power model for the processor IP and other major IPs, while the second phase involves a power abstract interpretation method for summarizing the simulation trace, then with a CPE module estimating the power consumption based on the summarized trace information and the input of IP power models.
In addition, a Manager component is devised to
map each DSP component to a host thread
and maintain the access to shared resources. The aim is to
maintain the simulation performance as the number of
simulated DSP components increases.
A power-profiling API is also supported
that developers of embedded software can use to tune the granularity of power-profiling
for a specific code section of the target application.
We demonstrate via case studies and experiments how application developers can
use our SID-based power simulator for optimizing the power consumption of their applications.
We characterize the power consumption of DSP applications with the DSPstone benchmark and discuss how compiler optimization levels with SIMD intrinsics influence the performance and power consumption. Also, we evaluate a wide range of multicore applications to demonstrate how our power simulator can be used by developers in the optimization process to illustrate different views of
power dissipations of applications. Finally, we summarize the major contributions of this thesis as follows:

- We propose a SID-based heterogeneous multicore power simulator. We incorporate two processors
into the virtual platform to simulate a heterogeneous multicore system: a 32-bit Andes processor
and a PAC-DSP. Our design allows simultaneous simulation of multiple PAC-DSP components by using a parallel
simulation approach. A PAC Manager component is devised to map each PAC-DSP component to a host thread and maintain the accessing of shared resources. This makes it possible to maintain the simulation performance as the number of simulated PAC-DSP component increases.

-We construct the power model of each target system IP includes, the Andes processor, PAC-DSPs, memory subsystem,
interconnection, and DMA. Hence our power simulator allows a full system simulation with power estimation support
for these targeting IPs that used in the virtual platform.

-We also propose a power-profiling API to help developers of embedded software to tune the granularity of power-profiling for a specific code section of the target application.

-We evaluate a wide range of DSP and multicore applications that include DSPstone, dual-core FIR application, multicore RMS, and vehicle detection application, in order to demonstrate how application developers can use our power simulator to exploit power optimizations in their applications.

參考文獻

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