內嵌穿晶片導線三維晶片模組之熱應力分析及最佳化

Thermal Stress Analysis and Optimization of 3D Chip Module

洪東銘(Dong-Ming Hong)

指導教授 ： 葉孟考

國立清華大學/工學院/動力機械工程學系/碩士(2008年)

摘要

利用系統整合的技術，如系統級封裝(System in Package, SiP)及系統單晶片(System on Chip, SoC)技術，可將不同功能之元件整合於單一晶片中，成為可提供多功能之封裝元件，然而微小化晶片使得散熱與結構之應力問題更為嚴重。本文主要探討三維影像處理晶片模組之熱應力問題，此晶片為採用穿晶片導線(Through-Silicon Via)佈線結構，由於在晶片內部因熱膨脹係數不匹配而產生應力集中現象。由於此晶片結構較為複雜，因此本文先針對晶片中影像感測模組部份，利用有限單元法進行熱-結構分析與幾何參數研究，以作為分析三維多晶片模組之參考依據，並利用紅外線熱像儀量測晶片表面溫度場，以驗證數值模型之正確性；接著本文以有限單元法模擬受熱負載之三維多晶片模組之結構穩態溫度與應力分佈。為減低結構之熱應力，本文以反應曲面法與田口法探討能有效提昇整體結構可靠度之最佳化設計，並比較兩種最佳化設計方法之差異性。

關鍵字

穿晶片導線 ； 熱應力 ； 最佳化

並列摘要

System in Package (SiP) and System on Chip (SoC) technologies are used to integrate different functional devices into one chip. The smaller the packaged device is, the more important the heat management and mechanics analysis of electronic packaging are. In this work, the steady-state temperature distribution and the corresponding thermal induced stress of the 3D chip with embedded copper through-silicon vias (TSVs) for image processing were analyzed by the finite element method. The finite element software was first used to investigate the effect of the dimensions of the chip with image sensor device under thermal loading. Temperature distribution of a 3D chip was also measured by a noncontact infrared thermography system to verify the numerical model. The steady-state temperature distribution and the corresponding thermal induced stress of the 3D Multi-Chip Module (MCM) with copper vias was simulated by the finite element method. The response surface method (RSM) and the Taguchi method were developed to determine the optimal dimensions of a the chip, such as pitch, diameter and depth of TSV, which can effectively reduce the thermal stress and enhance the structural reliability of the 3D chip module.

並列關鍵字

Through-silicon via ； Thermal stress ； Optimization

參考文獻

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