- 學位論文
具三向閘極奈米線結構雙複晶矽薄膜電晶體非揮發性記憶體的研究
Study of Twin Poly-Si Thin Film Transistors nonvolatile memory with Tri-Gate Nanowires Structure
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摘要
低溫複晶矽薄膜電晶體由於廣泛的應用在主動陣列液晶顯示器(AMLCD)和有機發光二極體而受到高度的矚目，且其不僅能當作一般的陣列開關，亦能應用於如靜態隨機存取記憶體(SRAM)，影像感應器(Linear image sensor)和非揮發性記憶體等。此外，由於電路的集積度不斷的增加，系統整合在面板上是未來的的趨勢，即將週邊電路，關鍵元件，驅動電路等整合在玻璃基板上。低溫複晶矽更是其關鍵技術。而非揮發性記憶體已經發展三十年餘，其在半導體工業中所扮演的角色也愈來愈重要。在本論文的第一部分提出具三向閘極奈米線結構雙複晶矽薄膜電晶體非揮發性記憶體，實驗果指出，具三向閘極奈米線結構的元件比單通道結構的元件有更優越的電性，由於奈米線結構有較多的轉角數目，其三向閘極的額外轉角電場使元件有更好的閘極控制能力，增加了元件的寫入及抹除效率。此外，本論文亦製作了不同閘極長度及不同耦合比的元件，探討在不同尺寸及不同耦合比的元件在電性上的影響。研究指出複晶矽的晶粒邊界缺陷對於薄膜電晶體的電性會有劇烈的影響，因此降低晶粒邊界缺陷可以改善薄膜電晶體的特性。在本論文的第二部分提出具氨電漿保護的雙複晶矽薄膜電晶體非揮發性記憶體，氨電漿保護可以降低晶粒邊界的陷井狀態密度，提升元件性能，可增加記憶窗口(memory window)，降低操作電壓，減少寫入抹除時間，並提高儲存時間。
關鍵字
奈米線並列摘要
In recent years, low-temperature polycrystalline silicon thin-film transistors (poly-Si TFTs) have drawn much attention because of their widely applications on active matrix liquid crystal displays (AMLCDs) , and organic light-emitting diodes (OLEDs) . Furthermore, low-temperature poly-Si TFTs will help to carry out the three-dimensional integrated circuits (3D-ICs) or multilayer Si ICs for system-on-chip (SoC) applications and fully functional system-on-panels (SoPs) in the future.It means that periphery circuits, key devices, and driving circuits all integrated on glass substrate. And nonvolatile memory (NVM) have been manufactured over thirty years, it has been becoming more and more important in the semiconductor industry because of their widely application for data storage. Based on previous experimental results, the NWs poly-Si TFT has the superior electrical characteristics due to the tri-gate structure and additional corner current induced by corner effect. In first part of this thesis proposed the twin poly-Si thin film transistor nonvolatile memory with tri-gate nanowires (NWs) structure. The experimental results show that the NWs device has superior electrical characteristic than the single channel (SC) one. Since the crowding of the gate fringing field at the narrow channel surface of NWs causes the large electrical field, the NWs devices with have the better gate control ability. The high electrical field verified enhancement of P/E efficiency in twin poly-Si TFT NVM due to the corner effect. Besides, this thesis demonstrated the different gate length and different coupling ration devices to discuss the coupling ration effect and floating gate length effect. The presence of polysilicon grain boundary defects in the channel region of TFTs drastically affects the electrical characteristics. Reducing the number of polysilicon grain boundary defects will improve the performance of poly-Si TFTs. NH3 plasma passivation has been reported to reduce the number of trap–states in poly-Si grain boundaries, yielding high-performance poly-Si TFTs. Thus, in the second part of this thesis, the twin poly-Si TFT NVM with NH3 plasma passivation is demonstrated. NH3 plasma passivation present better electrical characteristic, increase memory window, improve retention and decrease operation voltage.
並列關鍵字
HASH(0x1bc55980)參考文獻
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