高介電閘極氧化層之次奈米等效厚度於矽與砷化銦鎵半導體上之研究

The Study of Sub-Nanometer Equivalent Oxide Thickness of MBE and ALD Grown High κ Gate Dielectrics on Silicon and In0.53Ga0.47As Substrates

李昆育(Kun-Yu Lee)

指導教授 ： 郭瑞年 ； 洪銘輝

國立清華大學/工學院/材料科學工程學系/博士(2008年)

摘要

本實驗探討以分子束磊晶技術(Molecular beam epitaxy, MBE)與
原子沈積技術(Atomic layer deposition, ALD)成長的高介電閘極氧化層於矽基板與砷化銦鎵基板上之金屬-氧化物-半導體(Metal oxide
semiconductor, MOS)電容特性，並藉由降低氧化物與基板間的低介電層厚度使整體電容元件達到次奈米的等效厚度。在矽基板方面，藉由使用MBE 成長的高介電氧化鋁(Al2O3)與氧化鉿(HfO2)薄膜做為ALD 的孕核層可以有效抑制ALD 成長Al2O3 與HfO2 時介面層的生成。高解析度X 光光電子光譜儀(High resolution X-ray photoelectron spectroscopy, HR-XPS)與高解析度穿遂式顯微鏡
(High resolution transmission electron microscopy, HR-TEM)證實極少的介面層存在。ALD-Al2O3(1.9nm)/MBE-Al2O3(1.4nm) 與ALD-Al2O3 (3.0nm)/MBE-HfO2(2.0nm)的電性結果分別顯示介電值 (Dielectric constant, κ) 為9.1 與11.5、等效厚度(Equivalent oxide thickness, EOT)為1.41 與 1.7nm、介面缺陷捕捉密度 (Interface trap density, Dit) 為2.2 與 2×1011 cm-2eV-1、漏電流密度為2.4×10-2 與1.1×10-4 A/cm2。此外，我們也使用ALD-HfO2 (1.4nm)/MBE-HfO2 (1.5nm)的結構以提升ALD/MBE 複合閘極層的介電值並降低整體電容的等效厚度。κ 值達到16.2、EOT 為0.7nm、漏電流密度為5.3×10-1 A/cm2、Dit 為3.6×1011cm-2eV-1。良好的電性結果顯示極少的低介電層串連在氧化物與半導體介面。

在砷化銦鎵基板方面，我們研究以Hf(NCH3C2H5)4 (TEMAH) 與
H2O 做為ALD 前驅物直接成長HfO2 於暴露在大氣的In0.53Ga0.47As
/InP (100)晶片。結果顯示氧化物與基板的介面陡峭並且無元素砷或氧化砷存在，造成費米能階不被釘拴(Fermi level un-pinning)。藉由同步輻射AR-XPS 的量測結果，顯示只有Ga2O3, In2O3 與 In (OH)3 存在
介面。7.8nm HfO2 的MOS 電容元件展現漏電特性為F-N 穿遂機制
(Fowler-Nordheim tunneling mechanism)，電流值為10-8 A/cm2。變頻
的電容-電壓曲線也展示良好特性，Dit 為2×1012 cm-2eV-1。導電帶能隙
差(conduction-band offset)由電流傳導數據算出為1.8±0.1 eV。
另外，我們ALD成長的閘極氧化層HfO2在In0.53Ga0.47As/InP (100)
晶片上也達到次奈米等效厚度。關鍵在於減少In0.53Ga0.47As/InP 磊晶晶片由MBE 系統傳送至ALD 系統過程中暴露在大氣的時間。藉由
HR-XPS 與 HR-TEM 的量測，降低晶片暴露在大氣的時間至10 分鐘
以內可導致較少介面層厚度的產生。Au/Ti/HfO2(4.5nm)/ In0.53Ga0.47As 的MOS 電特性顯示等效電容厚度(Capacitive effective thickness, CET)為1nm，並且有良好的漏電值3.8x10-4 A/cm2。其值在相同等效電容厚度下與二氧化矽比，優10 的8 次方倍。整體MOS 元件的介電值為17-18，Dit 為2×1012 cm-2eV-1。

關鍵字

原子層沈積 ； 分子束磊晶 ； 高介電氧化物

並列摘要

Metal oxide semiconductor (MOS) capacitors that incorporated high κ materials of HfO2 and Al2O3 are fabricated by Molecular beam epitaxy (MBE) and Atomic layer
deposition (ALD) on Silicon and InGaAs substrates. The achievements in this work are to minimize the thickness of the interfacial layer at oxide/semiconductor and attain
sub-nanometer equivalent oxide thickness (EOT) value in the MOS diodes. In Silicon phase, MBE grown high κ dielectrics of Al2O3 and HfO2 are employed as templates to suppress effectively the oxide/Si interfacial layer formation during the subsequent ALD Al2O3 and HfO2 growth. The nearly absence of the interfacial layer was confirmed using angle-resolved x-ray photoelectron spectroscopy (AR-XPS) and
high resolution transmission electron microscopy (HR-TEM). The first two composite films consisting of ALD-Al2O3(1.9nm)/MBE-Al2O3(1.4nm) and ALD-Al2O3(3.0nm)/
MBE-HfO2(2.0nm) showed overall dielectric constant (κ) of 9.1, 11.5; EOT of 1.41, 1.7nm; interface trap density (Dit) of 2.2, 2×1011 cm-2eV-1; and a leakage current density of 2.4×10-2 A/cm2 at VFB-1V and 1.1×10-4 A/cm2 at VFB+1V, respectively. In addition, to further enhance the dielectric constant and reduce the EOT value of gate
oxide, the ultra-thin composite film with structure of ALD-HfO2(1.4nm)/MBE-HfO2(1.5nm) has been employed and demonstrated a κ value of 16.2, an EOT of 0.7 nm with a leakage current density of 5.3×10-1 A/cm2 at VFB-1V and Dit value of 3.6×1011 cm-2eV-1 at mid-gap calculated by conductance method. The attainment of high dielectric constants in these composite oxides suggests that no low κ capacitor in series near the oxide/Si interface.
In III-V phase, ALD grown high κ dielectric HfO2 films on air-exposed In0.53Ga0.47As/InP (100), using Hf(NCH3C2H5)4 (TEMAH) and H2O as the precursors,were found to have an atomically sharp interface free of arsenic oxides, an important aspect for Fermi level un-pinning. A careful and thorough probing, using high-resolution AR-XPS with synchrotron radiation, however, observed the existence
of Ga2O3, In2O3, and In(OH)3 at the interface. The current transport of the metal-oxide-semiconductor capacitor for an oxide 7.8 nm thick follows the Fowler-Nordheim tunneling mechanism and shows a low leakage current density of
~10-8 A/cm2 at VFB+1V. Well behaved frequency-varying capacitance-voltage curves were measured and an interfacial density of states of 2×1012 cm-2eV-1 was derived. A
conduction-band offset of 1.8±0.1 eV have been determined using the current transport data.
A capacitive effective thickness value (CET) of 1.0 nm has been achieved in ALD high κ dielectrics HfO2 on In0.53Ga0.47As/InP. The key is a short air exposure
under 10 min between removal of the freshly grown semiconductor epi-layers and loading to the ALD reactor. This has led to minimal formation of the interfacial layer
thickness, as confirmed using HR-XPS and HR-TEM. The measured electrical characteristics of metal-oxide-semiconductor diodes of Au/Ti/HfO2(4.5nm)/In0.53Ga0.47As showed a low leakage current density of 3.8x10-4 A/cm2 at VFB+1V,which is about 8 order of magnitudes lower than that of SiO2 with a same CET. The capacitance-voltage curves show an overall κ value of 17-18, a nearly zero flat band
shift, and an interfacial density of states Dit of 2×1012 cm-2eV-1 at mid-gap.

並列關鍵字

Atomic layer deposition ； Molecular beam epitaxy ； high k dielectrics

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