本篇論文的主題為設計一個完全數位控制之二進制頻移鍵控調變的射頻發射器電路,並且適用於頻率範圍落在2.4-GHz下之無線通訊傳輸應用產品上。有別於以往傳統經由類比的電壓訊號來控制振盪頻率的振盪器電路,改採用一個帶有三級之切換式電容陣列的數位式振盪頻率控制振盪器電路作為這個二進制頻移鍵控調變射頻發射器系統的主要核心部分。在此頻移鍵控調變射頻發射器電路系統中,有兩組數位控制的回授迴路系統來控制數位式頻率控制振盪器的輸出頻率,以實現二進制頻移鍵控調變的數位通訊傳送。在作二進制數位資料調變傳送之前,代表邏輯0與邏輯1的輸出頻率所需要的數位控制振盪器頻率控制碼由一組使用二元搜尋演算法的數位控制迴路來產生並儲存起來。在二進制數位資料作頻移鍵控調變並傳輸時,另一個數位控制的相位鎖定控制迴路啟動,以將因為長時間的操作之下導致的輸出頻率偏移量消除。整個發射器電路系統經過模擬後利用台灣積體電路公司的互補式金屬-氧化層-半導體0.18微米混合訊號製程來實現,整個晶片的面積大小為1.1 × 1.1平方微米。根據模擬後的結果,射頻發射器輸出的頻率範圍大約落在2.36 ~ 2.59 GHz之間,而相位雜訊的部分在偏離中心的載波頻率500 kHz位移處約在-110 dBc/Hz的雜訊程度附近。另外,在250-kHz的資料傳輸速率下,輸出的頻率平均誤差可小於100-kHz。整體功率消耗在1.8 V的電壓供應下約為13 mW。
This thesis presents the design of a fully digital controlled binary frequency-shift- keying (BFSK) RF transmitter for 2.4 GHz wireless applications. Instead of traditional voltage controlled oscillator (VCO), a digitally controlled oscillator (DCO) with three switched-capacitor arrays adopts as a core of this RF transmitter. There are two digital feedback loops to control the DCO to perform the BFSK transmission. Before data transmitting, the DCO codes for both logic-1 and logic-0 frequencies are generated and stored by a binary-searching digital calibration loop. When data modulating and transmitting, another digital phase-locked loop (PLL) is enabled to cancel the frequency shift induces by long-time operation. The designed transmitter is implemented in TSMC 0.18 μm CMOS process, and the chip area is 1.1 × 1.1 mm2. According to the simulation results, the frequency tuning range is around 2.36 ~ 2.59 GHz. The phase noise is about -110 dBc/Hz at 500 kHz offset frequency. For 250-kHz data-rate transmission, the frequency error is less than 100 kHz. The total power consumption is around 13 mW under 1.8 V power supply.