具功率意識之元件庫應用:組合邏輯電路設計

Cell Library for Power-Aware Applications: Combinational Circuit Design

林柏廷(Bor-Tyng Lin)

指導教授 ： 馬席彬

國立清華大學/電機資訊學院/電機工程學系/碩士(2008年)

摘要

隨著半導體製程技術的不斷演進，金氧互補式半導體(CMOS)的尺寸縮小至百奈米以下，同時數位電路之核心供給電壓也下降到一伏特甚至以下。然而對於一般的數位電路設計者而言，要將數千萬或上億顆的邏輯閘進行人工的設計是不可行的，因此標準元件設計流程(Cell-based design flow)便取代傳統流程成為市面上主流的數位電路設計標準流程。

本論文為數位電路設計者提供了一具有功率意識且可執行雙重電壓配給技術之標準元件庫以及流程設計。標準元件庫的設計除了需要耗費龐大的人力與時間之外，也需要額外的技術支援才能將目前已發展健全之低功率電路設計技術完全導入其設計流程中。在前端邏輯單元中，此元件庫挑選出具有較低消耗功率之運算架構單元，並且針對各種組合電路元件發展出一套簡化之最佳化流程。

為了有效降低數位電路之總體功率消耗包含動態功率和靜態功率，大範圍的調降供給電壓為此元件庫環境設計的重點之一。同時，不同臨界電壓之標準元件庫也可進行混用，以利於優化電路要求時序之合成結果。另外，在元件設計流程中依據 power efficient 的電路觀念，在單一晶片設計中運用此元件庫也可分別針對不同操作頻率之模組進行個別的供給電壓的規格支援。

測試電路使用國家晶片中心(CIC)所提供之資源進行晶片下線驗證，根據電路之模擬結果，使用本研究所設計之元件庫進行數位電路合成之通道估測器測試電路可在雙重供給電壓(VCC=1.0V, VCCL=0.6V)下，操作在50 MHz以上，此頻率超過原始IEEE 802.16e所制定之 throughput 標準，並且比原始電路節省趨近於70%之功率消耗。

關鍵字

標準元件庫 ； 低功耗 ； 低電壓 ； 最佳化

並列摘要

In modern digital integrated circuit, high performance design with low power dissi-
pation has been accomplished nowadays as the feature size of transistor keeps scaling
down. However, adopting low power techniques to the digital circuit design is crucial
and difficult in engineering practice at current stage. Cell-based flow is the most pop-
ular design flow in the various customized IC design market. Based on these fact, we
proposed a simple cell optimization flow to develop a cell library which enable a low volt-
age operation under 1.0V. Meanwhile, voltage scaling and multi-VCC partitioning low
power technique are also adopted to the modified cell-based design flow. For the isola-
tion between different power domain, the library based macro design is implemented for
the test circuit. By separating power nets into individual voltage block, two independent
regions are provided by each corresponding supply voltages.
According to the simulation results, by using the low voltage library and power
reduction methods merged to the designed flow, a power reduction compared with the
original test circuit approaching 70% can be achieved. Moreover, the test design can
provides two self-defined voltage blocks and voltage scaling options (VCC=1.0V-0.8V;
VCCL=1.0V-0.6V) without any performance degradation.

並列關鍵字

Standard Cell Library ； Low Power ； Low Voltage ； Optimization

參考文獻

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