矽晶穿孔結構之熱應力分析

Thermal stress analysis for through silicon via structure

郭騏緯(Chi-Wei Kuo)

指導教授 ： 蔡宏營

國立清華大學/工學院/動力機械工程學系/碩士(2012年)

摘要

近年來，三維立體晶片整合(3D Integration)是一項相當具有發展潛力的一項關鍵技術，不但可提高系統式封裝的密度，並可達到異質晶片之整合。其中矽晶穿孔(Through Silicon Via, TSV)結構是用以連結不同層之晶片的內部線路，但是晶片之散熱方式及其TSV材料間的熱膨脹係數不匹配，所以在往覆的溫度熱循環測試之負載之下，會有應力集中(Stress Concentration)的現象發生，導致結構發生破壞行為降低電子元件的可靠度。
本論文利用有限元素軟體ANSYS®進行TSV結構之力學模擬分析，針對具有矽晶穿孔之陣列及TSV接合部位的晶片堆疊結構受到加速熱循環測試極限溫度附載時之熱應力模擬，針對其結構幾何參數進行探討並分析其應力發生原因。另外，並將參數化分析的結果搭配實驗設計中的因子設計法(Factorial Designs)，進行該結構的變異數分析，找出影響應力最顯著之設計因子。
根據分析之結果，TSV陣列熱應力模擬結果顯示，在TSV空孔邊緣之金屬鎳會受到熱膨脹而拉伸或是收縮，使得此處產生最大應力。另外，在二氧化矽與矽的接面也會有應力產生，可能會使材料間發生脫層。此外在TSV參數分析中，減小墊片尺寸最能有效降低熱應力並且根據模擬結果也發現，降低填孔直徑比例與增加TSV之間距也可有效降低其應力。利用以上結果，本研究將得到在TSV陣列中之熱應力分布情形，並可用以找出TSV結構發生破壞的位置。

關鍵字

矽晶穿孔 ； 有限元素分析 ； 加速熱循環測試 ； 變異數分析

並列摘要

Recently 3D chip integration is an emerging technology. It can achieve high package density and integration of heterogeneous chip. Through silicon via provides vertical interconnections between stacking dies in 3D chip integration. However, there are still some challenges for this technology such as heat dissipation of 3D chip and large differences of coefficient of thermal expansion (CTE) in TSV structure. Due to the large thermal mismatch, the thermal stress at the interface of materials may result in the reliability problem of chip.
In this study, the thermal-mechanical stress distribution of a three dimensional TSV array model and bonding pad of TSV structure under the condition of accelerated thermal cycling loading is investigated by finite element analysis software-ANSYS®. Furthermore, the effect of geometry parameter of TSV to thermal stress is studied and analyzed by factorial designs and sensitivity analysis. According to the simulation result, the nickel at the TSV structure annular edges is stretched at 125 ﾟC and contracted at -40 ﾟC by the thermo expansion of other material, so the maximum thermal stress occurs at the nickel. Besides, the stress also occurs at the interface of silicon and silicon dioxide which may result in failure or delamination of TSV pads. In addition to, the parametric sensitivity analysis result shows that reducing the pad diameter is the most effective way to lower the thermal stress. Reduce the diameter ratio and increase the pitch between TSV can also lower the thermal stress. With these results, this study helps to obtain a clear thermal stress distribution of TSV array and possible failure regions in the TSV structure.

並列關鍵字

Through silicon Via ； Finite element analysis ； Accelerated thermal cycling test ； Analysis of variance

參考文獻

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