- 學位論文
具矽奈米晶體之環繞式閘極超薄多晶矽P型電晶體和記憶體的研究
Gate-All-Around Ultra-Thin P-channel Poly-Si TFT Functioning as Transistor and Flash Memory with Silicon Nanocrystals
摘要
此篇論文的研究主題為具矽奈米晶體之環繞式閘極超薄複晶矽奈米線P型電晶體和快閃記憶體的研究，論文中提出簡易且不需額外光罩的超薄主動層製作方式。本篇使用環繞式閘極之奈米線以及超薄主動層結構來增強閘極控制能力，抑制短通道效應，降低漏電流。其中有三種結構的比較，分別為：邊緣主動層厚度為超薄3nm且為Ω閘極形狀的平面結構，主動層為超薄厚度5nm環繞式閘極矽奈米線，以及主動層厚度為25nm的三向閘極結構。其中邊緣主動層厚度為超薄3nm且為Ω閘極形狀的平面結構，其特性次臨界擺幅(subthreshold swing)可達88mV/decade，電流開關比(On/Off current ratio)可達108。 對於記憶體而言，環繞式閘極還有增強穿隧氧化層電場和抑制閘極注入的優點，但是增強穿隧氧化層電場會使元件的可靠度下降。因此，應用矽奈米晶體為電荷儲存層以增加記憶體的可靠度；由於矽奈米晶體與氧化矽的傳導帶差值大於氮化矽與氧化矽的傳導帶差值，所以更增加此元件資料保持能力。本篇亦包含Ｐ型快閃記憶體操作方式，分別為FN穿隧以及帶隊帶穿隧的比較。其中顯示相較於FN使用大電壓穿隧，帶對帶穿隧可利用低電壓操作來使電子注入，而且同時兼具良好的可靠度。 超薄主動層具有陡峭的次臨界擺幅，高的電流開關比，較不明顯的汲極電壓引發通道位能障璧降低之效應(DIBL)，較大的驅動電流。其中邊緣為Ω閘極形狀的平面結構，以及環繞式閘極矽奈米線具有快速寫入速度還有良好的可靠度。本文所提出的超薄主動層製作方式，製程簡單且不需要額外光罩，並符合目前快閃記憶體的製程，顯示出擁有成為未來3D高密度快閃記憶體的潛力。
並列摘要
A novel Gate-All-Around (GAA) Ultra-Thin Body (UTB) P-channel poly-Si TFT functioning as transistor and flash memory with Silicon-Nanocrystals (NCs) have been successfully demonstrated. The proposed fabrication to form UTB is simple and without extra masks. Applying Gate-All-Around structure of the nanowires and Ultra-Thin Body structure enhance gate control ability, and suppress short-channel effects, including lowering the leakage. Three structures are compared, Edge Ω-gate planar with edge ultra thin 3nm-thickness body , GAA NW with ultra thin 5nm-thickness body, and Tri-gate NW with 25nm-thickness body. For the edge 3-nm-thick channel devices (the Edge Ω-gate planar), the S.S. can reach 88 mV/decade and Ion/Ioff ratio can achieve more than 108. To memory, using Gate-All-Around structure enhances the tunneling oxide electric field, and suppresses the gate injection. But with enhancing the tunneling oxide electric field, the reliability becomes worse. In order to improve reliability, silicon-Nanocrystals charge trapping layer is applied. Due to the difference of conduction band between Silicon-Nanocrystals and silicon oxide would be enlarged, so it has improved the data retention. The thesis is operating in p-channel Flash memory. The operations, including Fowler-Nordheim (FN) Tunneling and Band-To-Band Tunneling Induced Hot Electron Injection (BTBTIHE) are compared. And it shows extreme low applied voltage for band-to-band-tunneling-induced hot electron injection tunneling (BBHE) operation and excellent retention are proposed. The UTB devices are with steeper S.S., higher Ion/Ioff ratio, smaller DIBL and larger driving current than planar TFTs. The GAA and Edge Ω-gate planar structure with Si NCs NVM performs great P/E speed and good reliability. The process of the ultra-thin channel is simple with mask free and highly compatible with the current flash process, which is highly promised for the future 3D stacked high-density applications.
參考文獻
延伸閱讀
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