考慮可靠度之三維晶片設計

Reliability-aware 3D IC Designs

龍巧玲(Chiao-Ling Lung)

指導教授 ： 張世杰

國立清華大學/電機資訊學院/資訊工程學系/博士(2012年)

https://doi.org/10.6843/NTHU.2012.00494

摘要

三維晶片(3D IC)被視為可以突破製程微縮限製的重要技術之一。藉由穿矽孔提供貫穿晶片的垂直連線路徑而實現的三維晶片優勢包括較短的連線尺寸，較小的封裝面積，較高的晶片密度與異質整合彈性等。然而，可靠度的議題，如穿矽孔良率問題與過熱的堆疊晶片已成為三維晶片量產的主要障礙之一。為了解決上述議題，我們在這篇論文中提出了三個原創的方法，以提昇三維晶片設計的可靠度。
首先，我們提出一個可利用於三維時脈樹架構中的穿矽孔容錯架構。此一架構主要利用三維時脈網路設計中，堆疊前用來測試用的冗餘時脈樹，使得容錯所需的額外面積非常小。之後，我們針對三維多核心處理器，提出了一個熱導向的即時工作任務分配演算法。在這個方法裡，我們運用了漸近式的溫度分析，顯著的提昇了執行效能並得到準確度極高的結果。最後，我們又提出了一個應用於節能設計的電源模式感知時脈最佳化方法。相較於傳統設計中所使用的複雜而昴貴的技術，我們能以極少的成本達到同樣的目的。

關鍵字

三維晶片 ； 可靠度 ； 矽穿孔 ； 時脈樹 ； 容錯 ； 溫度 ； 節能設計

並列摘要

Three-dimensional integrated circuit (3D IC) is considered one of the most promising approaches at the limit of device scaling. The advantages of shorter interconnect lengths, smaller form factor, higher packing density, and the flexibility of heterogeneous integration, are realized by using through-silicon vias (TSVs) to connect the vertically stacking dies. However, the reliability issues, such as higher temperature effects and lower TSV yield rates, have become one of the major obstacles for 3D IC mass production. Furthermore, it is very arduous challenge to implement a single design to satisfy complicated clock tree constraints for an energy-efficient design with numerous operation power modes. To address the aforementioned issues, we originate three innovative ideas in this dissertation. First, for the issue of low TSV yield rate, a brand-new TSV fault-tolerant unit (TFU) is set forth to achieve yield improvement for the clock network of 3D ICs. The main idea is making use of a part of existing resources to lower the cost induced by establishing the fault-tolerant mechanisms. In the second work, we introduce a creative method, which significantly accelerate the speed of thermal simulation. By utilizing the method, we realize a real time thermal-aware task allocation, which can maintain the high accuracy property as well. Last, a power-mode-aware (PMA) clock skew optimization is presented for the energy-efficient designs. Instead of using complex and expensive methodologies, we merely using devices from the standard library to resolve the challenge of skew optimization in the energy-saving design. Thus, by utilizing the three innovative ideas, the robustness of 3D ICs can greatly improve.

並列關鍵字

3D ICs ； Reliability ； TSV ； Clock tree ； Fault-tolerant ； Thermal ； Energy-efficient designs

參考文獻

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