Cost Modeling and Analysis for Interposer-Based 3D ICs with 3D Memory Repair Schemes

基於矽中介層三維積體電路和三維記憶體修復的成本模型與分析

周盈妏(Ying-Wen Chou)

指導教授 ： 吳誠文

國立清華大學/電機資訊學院/電機工程學系/碩士(2012年)

https://doi.org/10.6843/NTHU.2012.00587

摘要

三維堆疊近來已成為一個積體電路相當流行的技術，而其中基於矽中介層的三維堆疊電路是在業界的主要趨勢，尤其是應用在處理器與記憶體的堆疊。去評估且找出基於矽中介層的三維堆疊最具經濟效益的測試流程是很重要的。我們提出了一個基於矽中介層的三維堆疊電路的成本模型，並且包括了晶片到晶圓 (D2W) 和晶片到晶片 (D2D) 兩種堆疊方式，成本裡也包含了製造成本和測試成本。我們將成本模型實作成成本分析工具，且使用此工具尋找最具經濟效益的測試流程。從結果我們可以發現，在某些應用中，測試流程若有包含反覆的堆疊測試 (iterative KGS test) 和矽中介層堆疊前測試 (pre-bond interposer test)，當堆疊良率低於99.2%和矽中介層良率低於99%時可以顯著地減少成本。另外也描繪了一個Shmoo圖表示在不同產品良率以及堆疊晶片顆數下所需封裝測試良率的底限。而三種不同的三維記憶體修復方案的成本也做了比較，結果表示當備用晶片數目大於二十顆時，使用區塊層級備分記憶體 (macro level redundancy) 可以得到最低的成本。對於不同的應用，該模型可找出測試動作執行的標準以及計算出成本值，這也可以幫助工程師去找出最具經濟效益的測試流程與系統架構。

關鍵字

三維電路 ； 成本模型 ； 矽中介層 ； 測試 ； 良率 ； 記憶體修復

並列摘要

Three-dimensional (3D) integration has recently become a popular technology for integrated circuits (IC). 3D IC with the passive silicon interposer is currently the main trend in the industry, especially for processor-memory integration. Evaluating the economic efficiency of test operations in the interposer-based 3D IC thus is important. We propose a cost model for interposer-based 3D IC with 3D memory repair schemes, including the Die-to-Wafer (D2W) and Die-to-Die (D2D) stacking. The cost model contains the manufacturing cost and test cost. A tool which is based on the proposed cost model is developed. We use this tool for cost analysis and for finding the most cost effective test flow. The results show that, in some applications, test flows including the iterative known-good stack (KGS) test and the pre-bond interposer test significantly reduce the cost, when the KGS test yield is lower than 99.2% and the pre-bond interposer test yield is lower than 99%. The Shmoo plot is depicted to show the lower bound of the yield of the final package level test, given the number of stacked dies and the final yield. The total costs of three types of 3D memory repair schemes are compared. The result shows that, among three different 3D memory repair schemes, the macro level redundancy with over 20 redundancy dies has the lowest cost. For different applications, the proposed model evaluates the execution criterion or cost values, which helps the designers to determine the most cost effective test flow and the system architecture.

並列關鍵字

3D IC ； cost model ； interposer ； test ； yield ； memory repair

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