- 學位論文
直接取樣接收器之前端電路設計
A Direct Sampling Receiver Frontend Circuit Design
摘要
自從電晶體以及積體電路開始發展之後，現今社會已經越來越發達，並且對於高科技產品之仰賴日益增加，而當需求增加之時，製程技術也跟著提高，而製程技術的提高也使得之前無法做在同一顆晶片中之各功能電路得以實現在同一顆晶片中，這就是現在常聽到的單晶片技術(SoC)。 而拜單晶片技術所賜，雷達的接收機以及發送機甚至可以在同一顆晶片上完成，所以徹底實現了小尺寸的目的，而因為尺寸變小所以應用層面上可以更廣，例如在軍事發展上，飛機的雷達系統可以因為單一晶片的縮小而擴展至更精密的陣列式偵測;在保全系統中也可以利用雷達去偵測是否有物體在移動;以及對於現在開車人口數多的社會可以利用雷達系統提供防撞功能，有機會可以降低交通事故之比例;更可以因應現今人口老化之社會，利用雷達系統之功能提供居家照護，身體狀況檢測。 而在雷達系統接收器中，主要功能是將天線接收下來之訊號做放大並且提供一個好的雜訊抑制能力，並且對訊號做降頻以利後段電路之運作。本論文採用直接取樣接收器之架構，其中電路包含低雜訊寬頻放大器，取樣及保存電路，電壓緩衝器，可調變放大器，而低雜訊放大器為天線接收訊號後之第一級電路，故其必須要對訊號做一初步放大，並且要對整體系統提供一個很好的雜訊抑制能力，以確保訊號不會失真。經過放大後之訊號將交由取樣及保存電路做降頻之後再由後段的基頻電路做處理，本次設計的電路以台積電65奈米製程進行實現驗證。
並列摘要
When mosfet and integrated circuit began being developed, modern society has become increasingly developed ,and people rely on high-tech product much more than past. Following the increased demand for high-tech product ,process technology progress ,and the improvement of process technology also make every functional circuit can be achieved in the same chip which cannot be made in the same chip before ,and it’s SoC technique what we often heard. Thanks to SoC technique ,receiver and transmitter of radar even can be achieved in one chip ,so it fully reach the target of small size ,Thanks to the smaller size ,the application level of ICs can be wider .For examples ,in military ,the airplane’s radar system can be extended to more sophisticated array detection because of the narrowing of a single chip .In security system ,radar system can also be used to detect the movement of objects ,and in modern society the proportion of car population more than past ,people can use radar system to provide anti-collision function ,which has the opportunity to reduce traffic accidents .Moreover ,because of aging population in our world ,people can use radar system to provide home care and physical condition detection. In the receiver of radar system ,its main function is to amplify signal received from antenna and providing system good capability of noise rejection .Moreover ,it should reduce signal frequency in order to facilitate the operation of the backend circuit .In this thesis, the direct sampling receiver architecture is used ,in which the system contains a wideband LNA ,sample & hold ,voltage buffer ,VGA ,and LNA is the first circuit after antenna ,it must amplify signal preliminary ,providing system good capability of noise rejection to ensure signal is not distorted .The amplified signal after reducing frequency by sample & hold circuit will be referred to the baseband circuit in the backend of radar system to operate .The design of circuit in this time will be implemented to test and verify by TSMC 65nm process.