三維積體電路提升良率及高效能設計

Yield Improvement and High-performance Design in 3-D Integrated Circuits

陳福偉(Fu-Wei Chen)

指導教授 ： 黃婷婷

國立清華大學/電機資訊學院/資訊工程學系/博士(2014年)

https://doi.org/10.6843/NTHU.2014.00074

摘要

隨著製程技術的進步，半導體元件在同樣的單位面積下可以擺置更多的電晶體，其電流消耗也隨之提升。隨著製程技術和晶片功能的提升，二維(2 Dimensional, 2D) SoC(System on Chip)設計方法(Design Methodology)面臨許多技術上和成本上的挑戰：例如，嚴重的製程變異性(process variation- random dopant fluctuation, line-edge roughness, etc. )、高昂的光罩與晶元製造生產費用和即時的上市時程(time to market)。因此，如何在三維晶片架構下，開發出降低成本之設計是相當重要之議題，本篇論文提出在晶片測試降低壓降(IR-drop)、利用三維矽智財再使用(IP re-use)來設計時脈樹以及提出有效的三維矽穿通道修復架構來提升晶片生產之良率以及降低成本。

首先，隨著製程技術的進步和晶片複雜度的提升，延遲錯誤測試(delay-fault test)越來越受到重視。主要的原因來自在0.13um 以下更先進製程中，製造瑕疵(defect)對晶片帶來的影響大多與時序(timing)有關。為了確保電路能正常運作，同速測試(at-speed test)技術廣泛的使用在時序相關缺陷的偵測，其中在同速測試的技術中，最普遍採用為scan-test launch-off-capture 的架構。同速測試主要的方法就是引發邏輯閘(gate)的電位切換(switching)，來驗證這些電位切換所經過的路徑延遲(path-delay)是否違反晶片要求。因此在測試過程中，受測電路會產生高於一般運作時的電位切換。進而引起較嚴重的壓降現象，而壓降則會增加路徑延遲進而導致測試錯誤，這種因為測試所導致的晶片不正常動作則是一種誤判(false failures)，進而有可能導致測試失敗使得良率降 (yield-loss)。近年來，為了改善壓降的問題，有許多相關研究被提出。本篇論文發現X-filling 改善壓降的效果會限制於原始測試樣本(test pattern)中x-bit 的分布形，這是因為測試樣本中的x-bit 無法影響壓降嚴重區域的邏輯閘的值。因此，本篇論文將提出一個新的X-identification 的方法來尋找x-bit 其訊號傳遞的路徑可以經過壓降較嚴重的區塊，使得X-filling 可以利用而進一步改善壓降。

接著在三維晶片部分，時脈樹合成(clock tree synthesis)在三維晶片的架構下，除了需考量時脈偏移(clock skew)和時脈延遲(clock latency)之外，為了確保能個別晶片預先功能測試驗証成功後(Known Good Die, KGD)再封裝以達到減少封裝測試成本，所以每一個別晶片仍需要個別的時脈樹做預鍵測試(pre-bond test)。三維時脈樹合成必須考慮下列問題才能完成預鍵測試：每一晶層(tier) 必須建立完整的二維時脈樹(2D clock tree)以使每一晶層可以單獨完成預鍵測試、三維晶片亦必須建立完整的三維時脈樹(3D clock tree) 以完成『後封裝測試』(post-bond test) 和正常功能操作。不同於現有己發表的三維時脈樹合成研究，皆是針對三維晶片重新做全面性的時脈樹合成，為了在三維晶片設計上達成類似二維晶片矽智財重複使用(IP re-use)之設計概念，我們將針對已設計完成的二維晶片矽智財重複使用，設計合成其他層的晶片與已設計好的二維矽智財整合。研究的主要問題包括如何連接到已設計好之二維晶片矽智財重複使用，以減少預鍵(pre-bond)及後鍵(post-bond)的時脈偏移和時脈延遲。此技術不但大量降低開發設計和光罩(mask)成本，亦同時達成個別晶片可以做時脈樹之預鍵測試。

最後，在三維晶片中，矽穿通道是最重要的組成原件。矽穿通道提供在不同晶片堆疊層的邏輯閘(logic gate)之間的訊號傳遞。矽穿通道由於製程變異(process variation)影響：例如，溫度、精密度、物理及化學變化，會造成矽穿通發生瑕疵甚至無法正常運作使得三維晶片良率因此下降，因此，Hsieh et. al.,提出串成鍊狀結構達到提升修復機率目的，但由於矽穿通道面積相較於普通元件龐大，因此需考慮矽穿通道使用個數，因此，我們提出具有節省矽穿通道面積且達到相同修復機率之架構並且發展出適合的演算法來擺置冗餘矽穿通道。

關鍵字

三維晶片 ； 矽穿通道 ； 測試 ； 壓降 ； 良率 ； 時脈樹

並列摘要

With the advances of VLSI design technology, yield loss, manufacturing cost, and reliability are more and more important. To tackle these issues, the yield improvement, cost reduction, and reliability mechanisms methodologies are required. In this dissertation, X-identication method, re-use methodology, and architecture of fault tolerance are proposed to achieve these goals.

First, to reduce the yield loss in high-performance design, a physical-location-aware X-identication method is presented. To guarantee that an application specic integrated circuit (ASIC) meets its timing requirement, at speed scan testing becomes an indispensable procedure for verifying the performance of ASIC. However, at-speed scan test suers the test-induced yield loss. Because the switching-activity in test mode is much higher than that in normal mode, the switching-induced large current drawn causes severe IR drop and increases gate delay. X-lling is the most commonly used technique to reduce IR-drop effect during at-speed test. However, the effectiveness of X-lling depends on the number and the characteristic of X-bit distribution. In this dissertation, we propose a physical-location-aware X-identication which re-distributes X-bits so that the maximum switching-activity is guaranteed to be reduced after X-lling. We estimate IR-drop using RedHawk tool and the experimental results on ITC'99 show that our method has an average of 9.42% more reduction of maximum IR-drop as compared to a previous work which re-distributes X-bits evenly in all test vectors.

Second, a clock tree algorithm with methodology of reuse in 3-D IC is proposed. IP reuse methodology has been used extensively in SoC (System on Chip) design. In this reuse methodology, while design and implementation cost is saved, manufacturing cost is not. To further reduce the cost, this reuse concept has been proposed at mask and die level in three-dimension integrated circuit (3D IC). In order to achieve manufacturing reuse, in this dissertation, we propose a new methodology to design a global clock tree in 3D IC. The objective is to extend an existing clock tree in 2D IC to 3D IC taking into consideration the wirelength, clock skew and the number of TSVs. Compared with NNG-based method, our proposed method reduces the wirelength of the new die and the skew of the global 3D clock tree, on an average, 76:92% and 5:85%, respectively.

Finally, an architecture of TSV recovery by using test elevator TSV is proposed. In order to increase the yield of 3-D IC, fault-tolerance technique to recover failed TSV is essential. In this dissertation, an architecture of TSV recovery by using test elevator TSV is proposed. With the architecture, no spare TSV is required to be inserted in advance. Hence, no extra area incurs. TSV assignment algorithm based on min-cost maximum-flow is proposed taking into consideration the locations of functional TSV as well as test TSV, so that the total Half-Perimeter Wire Length (HPWL) of a 3-D IC design is eectively reduced. Experimental results show that the total wirelength of 3-D IC testing is improved by 20% in average compared to that of spare TSV approach.

並列關鍵字

Three-dimensional Integrated Circuits ； 3-D IC ； TSV ； Test ； IR-drop ； Yield ； Clock Tree ； ATPG

參考文獻

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