RESURF埋層對PN二極體特性在高壓功率元件應用之研究

Theoretical Analysis and Applications of a floating P-Buried Layer in High Voltage Power Devices

楊富智(Fu-Jen Yang)

指導教授 ： 龔正 ； 黃智方

國立清華大學/電機資訊學院/電子工程研究所/博士(2014年)

摘要

因二氧化碳排放量逐年增加所造成的氣候變化已經成為世界的一大問題。電力運用的優化是全球必要持續解決的一個課題。近年來開關式電源供應器， LED照明，電子安定器，馬達驅動器等對高壓積體電路在控制及提高電源能量轉換效率的需求，越來越顯著。橫向高壓半導體功率元件被廣泛應用在高壓積體電路設計以達到低功率消耗和高能量轉換效率的性能。許多新型元件結構不斷被發明以同時降低元件順偏時的導通電阻和增加元件逆偏時的崩潰電壓，以在電路運作時達到最低的功率消耗。其中，RESURF技術尤為普遍地被使用在各種高壓功率元件設計中。

在本論文中全面研究了一個p埋層於RESURF高壓橫向PN二極體中的設計方法，找出重要的元件參數，透過電腦模擬與實驗驗證來探討這些參數是如何影響高壓半導體元件的導通電阻和崩潰電壓，並進一步分析其物理機制。其中針對p埋層的垂直位置，水平位置，和摻雜濃度提出元件的優化設計準則，提供對崩潰電壓和導通電阻在進行最佳化權衡設計時的參考。依此設計法則所設計出的PN二極體，實驗結果顯示可達到30.7％的元件崩潰電壓提升。本論文將所了解的物理機制及元件設計準則進一步擴展到高壓橫向擴散金屬氧化物半導體場效電晶體 (LDMOSFET) 的設計應用上，二維電腦模擬顯示比傳統的RESURF LDMOSFET元件在源極側達到了4倍的表面電場降低及32 ％的崩潰電壓提升。實驗結果展現出所設計的高壓元件逼近理論的Baliga Power Law，導通電阻比現行所發表的接面隔離LDMOSFET元件表現出低了40％的優異性能。論文中也闡述了高壓LDMOSFET元件在幾何構造，場效電板及電荷守恒的設計要點。

另一方面，高壓元件的安全操作範圍 (SOA) 也是極重要的性能，因其決定電路操作的最大範圍及系統的穩定性。於元件導通狀態下，通常在汲極偏壓接近累增崩潰電壓時，會觸發源極端的寄生雙極性電晶體導通效應並造成導通崩潰，此現象限制了高壓元件的安全操作範圍。然而，依本論文提出的設計法則所設計的LDMOSFET突破性的抑制了因寄生雙極性接面所導致的導通崩潰，並有效利用元件Kirk效應在高壓操作區突破了元件因高飄移區寄生阻抗所導致的準飽和電流限制，飽和電流隨閘極電壓的增加而等比例增加。實驗數據顯示此性能的提升擴展了功率元件的安全操作範圍多達2倍以上。論文透過實驗量測數據及二維電腦輔助模擬來分析並驗證所討論之高壓元件安全操作範圍的提升現象及成因。

關鍵字

RESURF 埋層 ； 高壓功率元件 ； 高壓橫向PN二極體 ； 高壓橫向擴散金屬氧化物半導體場效電晶體

並列摘要

Climate change by carbon dioxide emission has emerged as a big issue of the world. The electrical power energy saving and optimization are necessary as a whole to be solved for a sustainable world. Recently high voltage integrated circuits (HVICs) have been receiving interest and becoming key technologies to improve power conversion and controls from the process of energy exchange and minimize energy loss for use in the various high-voltage (HV) applications, including switch-mode power supplies, LED lighting, electronic ballast, motor drivers. Lateral high voltage semiconductor power devices have been widely used in HVICs design to achieve low power consumption and high energy transfer efficiency. In recent years, there have been lots of efforts and new innovative device structures proposed to minimize the on-state resistance and conduction power losses while maintain the high blocking voltage of power devices. The design concept most commonly applied in modern high performance power devices is the RESURF (REduce SURface Field) technique.

In this thesis, important parameters of the p-buried layer of a high voltage RESURF PN diode are comprehensively analyzed and discussed in terms of effects on device performance, including breakdown voltage and specific turn-on resistance, Ron,sp. The key parameters are identified and guidelines for designing the vertical position, lateral location, and doping concentration of the p-buried layer are suggested to optimize the device turn-on resistance and breakdown voltage tradeoff. The experimental results demonstrate that the PN diode with the proposed p-buried layer optimization design can improve breakdown voltage by 30.7% but with very little (2.7%) sacrifice in the specific on-resistance Ron,sp. The physics mechanisms and device design guidelines discussed in this paper was further extended to the design of high voltage LDMOSFET (Laterally Diffused Metal-Oxide Semiconductor Field-Effect Transistor). Two-dimensional simulations displayed that, compared to conventional triple RESURF structure, the present device provides a 4-fold reduction in the surface electric field on the source side and a 32% improvement in blocking voltage. Experimental results demonstrate that the BV-Ron,sp figure of merit (FOM) approaches the ideal Baliga’s power law. The specific on-resistance shows superior 40% lower performance than published JI (Junction Isolation) LDMOSFET device families. The optimal charge balance and geometrical design to achieve the lowest specific on-resistance (Ron,sp) with the desired maximum high breakdown voltage are displayed and discussed by simulations and experiment results.

This thesis extends the investigation into device SOA (Safe Operating Area) in terms of p-buried RESURF designs. The device SOA (safe operation area) is crucial to the performance and robustness of circuit designs for switching power supply applications. When the drain bias (VDS) of the device approaches the avalanche breakdown voltage, a parasitic n-p-n bipolar turn-on at source side is usually occurred, which causes early on-state breakdown in the LDMOSFET and limits the SOA range. The LDMOSFET with the proposed p-buried layer optimization design shows effectively suppressing the parasitic n-p-n bipolar on-state breakdown and enhance increasing the SOA capability. By triggering a Kirk effect to start before parasitic bipolar turn-on in the LDMOSFET, the on-state drain current (IDS) breaks the traditional Quasi-saturation limit and is dramatically expanded to be almost proportional to VGS at high drain bias (VDS) area, which substantially increases both current handling capability and the SOA margin when the power device is transiently operating between on-state and off-state. The experimental result shows that the SOA of the present device is remarkably increased by over 2-fold, which much benefits the performances of circuit designs for switching power supply applications.

並列關鍵字

High Voltage Power Device ； RESURF ； High Voltage PN Diode ； High Voltage LDMOSFET

參考文獻

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