應用於生醫訊號之二階三角積分調變器及其低電壓低功率設計考量

A Second-Order Delta-Sigma Modulator for Biomedical Application and Low-Voltage Low-Power Design Considerations

許智涵(Chih-Han Hsu)

指導教授 ： 鄭桂忠

國立清華大學/電機資訊學院/電機工程學系/碩士(2014年)

摘要

近年來，隨著醫療技術的蓬勃發展，健康照護這個概念已經成為現今生醫領域中的重要發展方向，藉由現今蓬勃發展的電子技術，達成體積小、方便攜帶且可長時間記錄監測的目標。而這種類型的生醫電子系統，低電壓、低功率消耗即為其中非常重要的設計要求之一，而其中類比數位轉換器則扮演著生醫系統中重要的關鍵角色。
本篇論文即是提出一個應用於生醫訊號擷取裝置、可處理大多數生理訊號之2階三角積分調變器；整個電路採用TSMC 90nm MSG 1P9M製程實現，以輸入前饋式架構來降低積分器輸出擺幅，以及採用低靜態電流電流鏡運算轉導放大器(OTA)來降低輸出級電流，以降低整體系統的功率消耗。
整個二階輸入前饋式三角積分調變器操作在1V供電電壓，在10KHz的訊號頻寬、超取樣率為64倍的情形下，所設計的調變器可以達到訊號對雜訊比為66.91 dB、訊號對雜訊與諧波失真比為64.87 dB，相當於有效位元數10.48位元；整個電路的消耗功率為17.14 μW，效能指標為0.6 pJ/conv.，整個晶片(包含Pad)面積為0.75 mm2。
此外，為了更進一步地改善電路效能，論文中亦探討多種能夠更有效地達到低電壓、低功率消耗的技術，像是解決低電壓下開關無法有效導通的靴帶式開關、能夠解決低電壓開關問題且能降低一半功率消耗的切換式運算放大器技術，還有能夠降低一部分功率消耗且能縮小面積的運算放大器共用技術，並說明其設計上的考量，以期未來能夠更進一步改善電路效能。

關鍵字

三角積分調變器 ； 輸入前饋式架構 ； 低靜態電流電流鏡運算轉導放大器

並列摘要

In recent years, with the rapid development of medical technology, health care, this concept has been implemented by electronic technology to reach the targets such as small volume, portable, and long record data. Among these biomedical electronic systems, low voltage, low power consumption is one of very important design requirements. And analog-to-digital converter (ADC) plays a very important role in these systems.
This thesis presents the design and implementation of a second order delta-sigma modulator, which is applied to biomedical signal acquisition devices that can handle most of the physiological signals. The entire circuit is implemented with TSMC 90nm MSG 1P9M process, by using input feed-forward architecture to reduce the integrator output swing and low quiescent current current-mirror operational transconductance amplifier (OTA) to reduce output current for system low power consumption.
The 2nd order input feedforward delta-sigma modulator operating at 1V supply voltage, with 10KHz signal bandwidth, and oversampling ratio of 64, the designed modulator achieved signal to noise ratio (SNR) of 66.91 dB, signal to noise and distortion ratio (SNDR) of 64.87 dB, equivalent to the effective number of bits (ENoB) of 10.48 bits. The power consumption is 17.14 μW, the figure of merit (FoM) is 0.6 pJ/conv., and the entire chip area (including pad area) is 0.75 mm2.
In addition, this thesis is also to explore some low voltage, low power consumption technologies, such as bootstrapped switch, switched-opamp technique, and opamp-shared technique, and discussing their design considerations to further improve the circuit performances in the future.

並列關鍵字

Delta-Sigma Modulator ； Input Feedforward Architecture ； Low Quiescent Current Current-Mirror Operational Transconductance Amplifier

參考文獻

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[8] N. Oliver and H. K. Robert, "A 19-Bit Low-Power Multibit Sigma-Delta ADC Based on Data Weighted Averaging," IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 32, no. 7, July 1997.