- 學位論文
以紫外光奈米壓印技術製作塊材鰭狀鋁奈米晶粒快閃記憶體
Fabrication of Bulk FinFET Aluminum Nanocrystal Flash Memory by UV-Nanoimprint
摘要
本論文為整合UV奈米壓印微影技術，低溫微波退火技術，具熱流動性之類氧化矽HSQ作為塊材鰭狀場效電晶體之絕緣層，並且以鋁奈米晶粒作為快閃記憶體之浮閘極以製作塊材鰭狀鋁奈米晶粒快閃記憶體。在UV奈米壓印微影技術開發上，以HSQ作為可透光模仁材料，經過電子束微影劑量，曝後烤，與顯影條件最佳化後，可製作出線寬46 奈米，線寬/線距為1:1之高深寬比模仁。之後發展常溫低壓之UV奈米壓印微影技術用於奈米鋁線與鰭狀矽奈米線之製作。在記憶體製作上，利用本實驗室自組裝之RTA-MOCVD系統，以不破真空的方式連續沉積Al2O3/Al-rich AlOxNy/AlN 於SiO2/n-Si基板上。製作上，混合三甲基鋁和氨氣以不同的氣體流量比、溫度及壓力分別鍍製穿隧介電層(氮化鋁)、電荷儲存層及阻擋介電層(氧化鋁)於SiO2 / n-Si (100)基板上，其中在沉積電荷儲存層時，以不同沉積溫度，以研究鋁奈米晶粒大小與包覆絕緣層成分隨溫度之變化。在鰭狀場效電晶體，降低寄生電阻是一個重要的議題。通常，以高溫來修復因離子佈值產生的缺陷是必要的，但是垂直與側邊的摻雜擴散卻會造成元件的漏電。為了減少在活化時造成源/汲極的摻雜擴散，可運用低溫微波退火技術。為了要在奈米尺寸下準確的量測垂直的摻雜，首先，用硝酸, 氫氟酸, 醋酸混合為蝕刻溶液，調變不同蝕刻液濃度，選擇性蝕刻硼摻雜且活化之矽基板，找到蝕刻速率，以此方式檢測活化之輪廓。接著，以UV奈米壓印製作經過微波退火之鰭狀矽奈米線，用傳遞長度方法量測特徵接觸電阻值與矽奈米線之電阻率。在製作鰭狀矽奈米線時，需要有絕緣層以阻絕金屬電極和矽基板，本論文以具有熱流動性之類氧化矽HSQ作為絕緣層，經過簡單的旋塗與漸進式加熱，HSQ即可填入溝槽，即可取代傳統之化學機械研磨方法。由前述的實驗找到最佳微波退火條件，並將其應用在塊材鰭狀鋁奈米晶粒快閃記憶體的源/汲極活化。最後，整合UV奈米壓印微影技術，低溫微波退火技術，具熱流動性之類氧化矽HSQ作為塊材鰭狀場效電晶體之絕緣層，以閘極後製作方法，並且以鋁奈米晶粒作為快閃記憶體之浮閘極以製作出15 奈米鰭狀矽奈米線與150 nm閘極線寬塊材鰭狀鋁奈米晶粒快閃記憶體。
並列摘要
In this work, bulk Fin field-effect transistors (FinFET) aluminum nanocrystals (Al NCs) flash memory was proposed. It integrates UV-nanoimprint lithography (UV-NIL) for Si fin and gate length patterning, HSQ for isolation, microwave annealing (MWA) for source/drain (S/D) activation, and Al-based memory stacked layer. Al nanowire (NW) and Si fin fabricated by UV-NIL with HSQ stamps is developed. First, in order to pattern the high AR HSQ stamp on ITO/glass substrate, a low e-beam dose exposure combined with heat treatment is used for increasing SiO cross-linking density of HSQ films and enhancing the hardness of HSQ stamp. The antiadhesive layer coated HSQ stamp can be applied for UV-NIL with UV-curable photoresist layer (PAK). UV-NIL with low pressure at room temperature can make the imprinted pattern good replication fidelity with HSQ stamps. After UV-NIL, the patterned PR can be utilized to conducted lift-off or etching process. High aspect ratio of 2.5 with width of 46 nm and width:spacing=1:1 HSQ stamps can be obtained. The Al-base memory structure of Al2O3/Al-rich AlOxNy/AlN/SiO2/n-Si were deposited by rapid thermal processing metal organic chemical vapor deposition (RTP-MOCVD) method. The composition of Al2O3/Al-rich AlOxNy/AlN stacked layers were produced continuously without breaking vacuum by modulating the flow rate of trimethylaluminum (TMA) and ammonia (NH3) and deposition temperature. Furthermore, the Al-rich AlOxNy matrix was deposited at various temperatures to adjust the stoichiometry of AlOxNy to reduce trapped state generation during the stress cycling for good electrical performance. The P/E speed, retention time, and endurance cycling of memory devices were also investigated. We also performed low temperature MWA experiments with different anneal power and time to study the boron dopant profiles and the activation in Si fin. First, in order to characterize atomic and carrier profiles in Si p-n junctions, the secondary ion mass spectroscopy (SIMS) measurement is used to derive atomic concentration data. Further, the selective etching method by using HF-HNO3-CH3COOH (HNA) solution is used to obtain the activated dopant profile. The etching thickness is measured by atomic force microscope (AFM). So, the calibration of the etch rate of p-Si thickness as a function of the carrier concentration is established. The junction depth and the activated dopant profile can be obtained. Comparing with the SIMS data and activated dopant profile, the electrical activity can be found. Further, in order to investigate the electrical properties of Si fin NWs after BF2 implantation and MWA, the transfer length method (TLM) analysis was also employed to obtain the contact resistivity between Al/Ni metal and Si fin and resistivity of Si fin. For FinFET isolation between gate and Si substrate, the flowable oxide of HSQ is used by simple spin-coated method followed by step-like heating to remove solvent and change the molecular structure to SiO2-like material. During step heating process, the HSQ would fill in the trench between Si fins without the chemical mechanical polishing (CMP) process. Finally, the UV-NIL for Si fin and gate length patterning, HSQ for isolation, microwave annealing for S/D activation were integrated with gate-last method to fabricate bulk FinFET device. The Al-NC memory stacked layer of Al2O3(10 nm)/Al-rich AlOxNy(8 nm)/AlN(3 nm)/SiO2(2 nm) were deposited by RTP-MOCVD system on 15 nm Si fin. The final bulk FinFET Al NCs flash memory can be fabricated. The electrical characteristics are also investigated and correlated to SEM and TEM analysis of the device.