適用於低頻率低工作週期與次臨界區電壓下的電壓倍乘器操作模型

電壓倍乘器為一種可以將交流電壓轉為更高的直流電壓的升壓電路。其中的輸入訊號通常為一高於電晶體截止電壓的訊號，並且較適用於高頻率與固定工作週期。但有許多應用例如RF訊號與磁電能發電等低電壓訊號與低頻率訊號將是未來的主流方向，此篇論文將對於了許多關於低電壓低頻率與低工作週期的訊號是否能應用在電壓倍乘器上作一些討論與研究。　　目前的電壓倍乘器皆為基本型的Dickson所提出的升壓電路(Dickson charge pump)所做的改良，而許多基於此電路的模型亦必須適用於輸入訊號的電壓大於電晶體截止電壓的訊號。但若當輸入訊號的電壓小於電晶體截止電壓的訊號，則模型將無法使用，換言之，隨後的最佳化設計許應用將無法繼續使用。此篇論文研究了電壓倍乘器在充放電時的等效電路之後並提出，若將電晶體截止電壓的值代換為一等效參數，則此模型可以繼續使用於低電壓訊號。此篇論文並提出若將一震盪器置放於電壓倍乘器的前方，將訊號先行經過震盪之後再接入電壓倍乘器則可大幅提升輸出電壓，或者可降低晶片電容面積。最後，假設製程廠可以提供變化的截止電壓，則可根據變化後的截止電壓大幅提升震盪器的震盪頻率與電壓倍乘器效率，更能大幅提升電壓與降低晶片電容面積。　　此篇論文使用一低電壓低頻率低工作週期的真實磁電能發電訊號作為模型範例，其電壓為0.26伏，頻率為5赫茲，工作週期為12.5%。而其目標電壓為3.5伏並輸出1毫安培的電流。模擬條件皆基於台積電0.35毫米製程。

關鍵字

電壓倍乘器；低頻率；低工作週期；低電壓；次臨界區

並列摘要

Voltage multipliers, which boost a low AC voltage to a higher DC voltage, have many applications today. The input signals, if generated on chip, can have a relatively high frequency, large signal swing and a fixed duty cycle. On the other hand, if the input signal is taken from external RF sources or mechanically generated electrical signals, then the input can have a very low signal swing, low frequency or low duty cycle. This thesis studies how to apply the conventional voltage multiplier to these low voltage, low frequency and low duty cycle conditions. The conventional voltage multiplier (Dickson charge pump) has been studied extensively. A simple analytical model relates the output voltage to the input voltage has been derived. As long as the input signal has a swing larger than the transistor’s threshold voltage, the output voltage can be predicted using a simple equation. But when the input swing is much lower than the threshold voltage, then the equation breaks down. We find that we can extend the equation to lower input swings, if threshold voltage is replaced by an effective threshold voltage. To address the low frequency and duty cycle issues, pulse clustering effects are studied. It is also found that adding a ring oscillator to increase signal frequency is a very effective approach. If possible, optimizing transistor threshold voltage can increase output voltage, increase transfer efficiency or reduce chip area without additional cost. In this thesis, a real electromotive force signal is used as input signal. The amplitude of this signal is -0.26 (V) to 0.26 (V). The oscillation frequency is 5 (Hz) and the duty cycle is 12.5%. The objective output voltage is 3.6 (V) and output current is 1 (mA). All simulations are based on TSMC 0.35um CMOS models.

並列關鍵字

Voltage Multiplier ； Charge Pump ； Low Frequency ； Low Duty Cycle ； Low Voltage ； Subthreshold Voltage

參考文獻

[1]. John F. Dickson, “On-Chip High-Voltage Generation in NMOS Integrate Circuits Using an Improved Voltage Multiplier Technique,” IEEE Journal of Solid-State Circuits, vol. 11, sc-11, no. 3, June. 1976.

[2]. Hiu-Yeung Lo, Pui-Ying Or, Ka-Nang Leung, Lai-Kan Leung, Chiu-Sing Choy, and Kong-Pang Pun, “Design Challenges of Voltage Multiplier in a 0.35-um 2-Poly 4-Metal CMOS Technology for RFID Passive Tags,” IEEE Conference on Electron Devices and Solid-State Circuits, 2007.

[4]. Chenling Huang and Shantanu Chakrabartty, “Low-threshold Voltage Multipliers based on Floating-gate Charge-pumps,” IEEE Biomedical Circuits and Systems Conference, Nov. 2008.

[5]. Hiu Yeung Lo, Pui Ying Or, Ka Nang Leung, Lai Kan Leung, Chiu Sing Choy, and Kong Pang Pun, “Design Challenges of Voltage Multiplier in a 0.35-am 2-Poly 4-Metal CMOS Technology for RFID Passive Tags,” IEEE International Conference of Electron Devices and Solid- State Circuits, Dec. 2007.

[6]. Louie Pylarinos, “Charge Pumps: An Overview,” Department of Electrical and Computer Engineering, University of Toronto.

國際替代計量

適用於低頻率低工作週期與次臨界區電壓下的電壓倍乘器操作模型

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