提昇記憶體良率的彈性備援修復方案與先進備援分析方法

A Flexible Redundancy Repair Scheme and Advanced Redundancy Analysis Method for Memory Yield Enhancement

李旻昇(Lee, Mincent)

指導教授 ： 吳誠文

國立清華大學/電機資訊學院/電機工程學系/博士(2013年)

https://doi.org/10.6843/NTHU.2013.00161

摘要

記憶體修復隨著更多的系統晶片及高度整合的產品而需求大增，因晶片良率常取決於記憶體良率。但內嵌與標準型記憶體的備援修復方式相當不同。內嵌型常以晶片中有限的資源內建自動修復，因傳統外部測試太貴。而標準型比內嵌型更大而複雜，並有更多測試需求以因應各種系統應用。因此，他們通常以自動機台測試再修復，並內建更複雜的備援架構，也需要比內建自動修復更複雜的備援分析演算法。而自動測試機台非常昂貴。為了節省測試修復時間，商用機台無法以複雜的備援分析來支援完整的備援限制，也造成良率損失。
此論文提出基於正交限制演算法的備援配置工具。它高度可程式化以支援測試機台上各種記憶體。可由機台取出測得的瑕疵資訊，再產生修復配置給雷射修復機台。雖提出的線性時間啟發式備援配置演算法非最佳化，因這是非決定性多項式時間中最難的決定性問題，但它很有效的達到比原機台演算法更高的修復率。實驗中，提出的演算法能為原本的機台修復流程挽回22%的裸晶，有效的提升良率。為了探尋更多變的備援架構以進一步提升良率，也分析業界夥伴的記憶體瑕疵分布圖以研發評估修復方案。發展出先進的備援分析技術，包含瑕疵分布視覺化、數學模型評估、備援導向的涵蓋統計分析、關鍵必修分析、及修復率合併成本指標。
論文後半提出記憶體內建自動修復電路產生器，能為系統晶片設計師自動產生暫存器轉換語言層級的電路。根據備援必要樞紐配置演算法，及更彈性的備援架構，能調整相同的備援以更有效率的修復各種行列及區塊瑕疵。並以很小的電路支援全速測試，也不會造成時脈延遲。以一般0.13微米的互補式金屬氧化物半導體製程為例，512,000位元、333百萬赫茲的記憶體備有4個備援單元，僅有0.36%的面積額外負擔。以低面積、時脈額外成本，它能輕便的實現多記憶體的分散修復方案。比最近的研究，有更小的面積、又不多花測試時間。

關鍵字

內建自動修復 ； 動態隨機存取記憶體 ； 內嵌式記憶體 ； 標準型記憶體 ； 基礎設施矽智財 ； 記憶體修復 ； 記憶體測試 ； 備援分析 ； 備援配置 ； 系統晶片 ； 動態隨機存取記憶體 ； 良率提升

並列摘要

There is growing need for memory repair due to the introduction of more and more system-on-chip (SOC) and other highly integrated products (e.g., 3D-IC), for which the chip yield is being dominated by the yield of on-chip memories or known good dies (KGD) of commodity memories. The memory redundancy-repair schemes are quite different between commodity and embedded memories. Embedded memories are normally repaired by built-in self-repair (MBISR) schemes with only limited on-chip resource, be-cause repairing embedded memories by conventional off-chip schemes is too expensive. On the other hand, commodity memories are much larger and more complicated than embedded memories, and have much more test re-quirements to meet various applications and systems. Therefore, they are normally tested and repaired by an Automatic Test Equipment (ATE). The memory is designed with more complicated built-in redundancies, and may require more complex redundancy analysis (RA) algorithms as compared with MBISR. However, ATE is expensive. To reduce test and repair time, commercial ATEs cannot afford complex RA algorithms that consider the complete redundancy constraints. That results in certain degree of loss in repair rate, and thus yield.
In this thesis, we first propose a Memory Spare-Allocation tool called MESA, based on a Constrained-Orthogonal algorithm. It provides high programmability for various memories tested by ATEs. The tool obtains fault information from the ATE output, and then generates repair solutions for the memories to be repaired by the laser repair equipment. Although the pro-posed linear-time heuristic spare-allocation algorithm is not optimal, as the problem is NP-complete, it is quite efficient and achieves a higher repair rate than the original RA algorithms on the ATE. In one of our experiments, e.g., the proposed algorithm can rescue about 22% of the dies that did not pass the original ATE repair process, effectively improving the yield. To explore various redundancy architectures and further enhance the yield, we also analyze, develop and evaluate repair schemes with silicon failure bitmaps from our industry partners. We have developed advanced redundancy analysis methods, including bitmap visualization, mathematical estimation, redundancy-oriented coverage statistics and analysis, critical and must-repair analysis, and combined index of repair rate and overhead.
In the second part of the thesis, we propose an MBISR generator called BRAINS+, which automatically generates RTL-level MBISR circuits for SOC designers. The MBISR circuit is based on an RA algorithm that enhanc-es the Essential Spare Pivoting (ESP) algorithm, with a more flexible spare architecture, which can configure the same spare to a row, a column, or a rectangle to fit failure patterns more efficiently. The proposed MBISR circuit is small, and it supports at-speed test without timing-penalty during normal op-eration, e.g., with a typical 0.13 μm CMOS technology, it can run at 333 MHz for a 512 Kb memory with 4 spare elements (rows and/or columns), and the MBISR area overhead is only 0.36%. With its low area overhead and zero test-time penalty, the MBISR can easily be applied to multiple memories with a distributed RA scheme. Compared with recent studies, the proposed scheme is better in not only test-time but also area overhead.

並列關鍵字

Built-In Self-Repair (BISR) ； DRAM ； Embedded Memory ； Commodity Memory ； Infrastructure IP ； Memory Repair ； Memory Testing ； Redundancy Analysis ； Spare Allocation ； SOC ； SRAM ； Yield Improvement

參考文獻

[2] Semiconductor Industry Association, "International Technology Roadmap for Semiconductors (ITRS), 2011 Edition," Sematech, Incheon, Korea, Dec. 2011.

[3] Semiconductor Industry Association, "International Technology Roadmap for Semiconductors (ITRS), 2010 Edition," Sematech, Tokyo, Japan, Dec. 2010.

[4] Semiconductor Industry Association, "International Technology Roadmap for Semiconductors (ITRS), 2009 Edition," Sematech, Hsinchu, Taiwan, Dec. 2009.

[5] Semiconductor Industry Association, "International Technology Roadmap for Semiconductors (ITRS), 2008 Edition," Sematech, Seoul, Korea, Dec. 2008.

[6] S.-Y. Kuo and W. K. Fuchs, "Efficient Spare Allocation in Reconfigurable Arrays," IEEE Design & Test of Computers (D&T), vol. 4, pp. 24-31, February 1987.