奈米實體層設計的良率及可繞度提昇

Nanometer Physical Design for Yield and Routability Enhancement

張豐願(Fong-Yuan Chang)

指導教授 ： 蔡仁松

國立清華大學/電機資訊學院/資訊工程學系/博士(2013年)

https://doi.org/10.6843/NTHU.2013.00674

摘要

現今的積體電路奈米製程, 遇到了很多的限制. 為了提升良率,在積體電路實體層設計時, 需要考量到製程上所遇到的限制. 這些限制增加了實體層設計的困難度, 本篇論文針對這些限制提出了解決方案,能夠提升實體層設計的可繞度及製程良率. 本論文主要提出了三個技術. 第一的技技術是利用插入額外繞線來增加良率. 第二個技術是針對扁平的設計區塊, 提出方法來提昇繞線資源的利用率. 第三個技術是一個繞線時就能同時考量製程規則的最短路徑繞線方法. 經由實驗結果驗證, 這些方法可以有效的提升實體層設計的可繞度及製程的良率.

關鍵字

實體層設計 ； 繞線 ； 製程規則

並列摘要

In today’s nanometer IC (Integrated Circuit) processing, foundries are facing increasing challenges from process limitations that seriously impact the chip yield and reliability. To overcome these limits, numerous design rules are imposed by foundries to be followed in IC design, especially in physical design. Besides design rules, we need to handle some other manufacturing defects, such as wire opens and shorts, for higher chip yield rate. Thus, in this thesis we first introduce two techniques to deal with the process limitations. The first one focuses on handling design rules in maze routing. We propose a shortest path algorithm under nanometer design rules, called MANA. With the algorithm, most rule violations are prevented in maze routing instead of being resolved in post-processing. The second technique is to increase the chip yield by inserting redundant wires to tolerate wire opens. After completing the design routing, usually there are still remaining routing resources that can be used for redundant wire insertion. The proposed insertion algorithm can accurately consider the wire open and short simultaneously and guarantee yield increasing for each insertion. Besides the above two routing innovations, we also introduce a useful technique for routing resources allocation to improve routability. In current SoC (System on Chip), the aspect ratios of blocks in designs may vary much and the required resources in horizontal and vertical directions are different. Thus, we introduce an approach to allocate and consolidate routing resources considering directed routing resource demands, which can greatly increase routability especially for designs with thin areas. The goal for our proposed methods is to achieve high routability and chip yield for nanometer SoC designs.

並列關鍵字

Physical Design ； Routing ； Maze ； Redundant Wire ； Cut-Demand ； Nanometer Design Rule

參考文獻

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