- 學位論文
針對延遲缺陷及系統性製程變異之缺陷診斷系統
Delay Fault Diagnosis Techniques Targeting on Both Spot Delay Defects and Systematic Process Variations
摘要
在面對越來越多的設計挑戰，如高設計複雜度、未成熟的新製程技術、緊迫的上市時間壓力等等，設計工程師必須將診斷跟除錯都視為設計過程的一部分。然而，隨著設計的尺寸增加，診斷的難度及其所必須花費的時間也隨之快速增加。診斷工具是用來快速的縮小可能發生缺陷的區域及數量，在不倚賴十分耗時物理檢視工具來一一檢查所以可能發生缺陷的地點，以利加快檢查出讓晶片或製程發生問題的原因。在先進製程上，時序缺陷(Timing defects)可能來自於許多方面，如由塵埃引起的短路缺陷(Short defects) 、由不適當的設計規範(DFM rules)所導致的開路缺陷(Open defects) 、由光學系統的透鏡不完美性所引發的透鏡像差、離子佈植不均和由不良的化學機械研磨過程(Chemical-Mechanical Polishing)導致的線寬不均等因素。因此，要從這麼多可能的原因中準確地判斷是由哪一個步驟或是發生的位置是非常困難。 在本論文中，我們針對了單點延遲缺陷及由製程變異所導致的微小延遲偏差提出了一系列的診斷相關技術及軟體。我們提出的方法除了如傳統的診斷方法可能產生一缺陷發生可能位置排序表外，並能夠估計晶片內部各個元件所能達到的速度。我們利用了這個優點，根據這些估計出來的元件效能，我們開發了一套能夠推算出在此製程下的晶片內部的時序圖像(Timing profile)。另外，我們也引用了統計學習的觀念來分析診斷後的資料，並且得到造成此製程變異的最可能因素。利用我們所提出的針對每個元件的特徵編碼(Feature encoding)及特徵排序方法，我們可以有效的收集資料並得到這些偏差的元件最主要的特徵。從這些特徵我們可以在設計時避免掉某些會造成製程變異的因素。在只植入單一個單點缺陷的實驗中，我們的方法能夠達到1.96 的平均排名，亦即我們平均在前兩名就能夠找到缺陷所在。而我們也做了同時植入10 個延遲缺陷的實驗，其平均排名為1.43。另外，針對製程變異所造成的微小延遲偏差，我們所提出的方法能夠準確的估計出每個元件的延遲時間。在實驗中，我們計算其估計出來跟由製程變異模型取樣出來的元件延遲時間的相關性，平均能夠達到高達0.916 的相關性，效果十分良好。
並列摘要
Facing a multitude of design constraints: higher design complexity, immature new process technology, shrinking time-to-yield, etc., designers have to take debug and diagnosis as an integral part of the design process. Yet, imposed by the huge design size, efforts of diagnosis increase rapidly. Diagnosis tools are used to quickly shrink the number of defective candidates that helps to speed up the process without resorting to physical inspection tool for every possible suspect of faulty location. In advanced process, timing defects comes from several aspects such as dustinduced short, open defects induced by in inappropriate Design For Manufacturability (DFM) rules, lens aberration from lithography system, variation on dopant concentration or critical dimension from Chemical-Mechanical Polishing (CMP) process, etc. Therefore, it is getting more and more difficult to identify the main causes of timing failures from such a wide range of suspects. In this thesis, we propose a series of diagnosis methods targeting on not only spot delay defects but small delay variation induced by process variation. The proposed method is capable of estimating delays of segments in tested paths instead of just reporting the ranks of segments as the traditional diagnosis methods. With the capability, a timing profile for the process and the die under manufacturing can be extracted based on the estimated segment delays. Moreover, the causes of process variation can be concluded by applying machine learning techniques on diagnosis data. With the proposed feature encoding and ranking method, the main features of abnormal devices for a failing chip instance can be extracted. In the experiments, 1.96 of first-hit-rate (ranking of the injected defects) for single spot defects and 1.43 of first-hit-rate for 10 spot defects simultaneously injected can be achieved For process variation induced small delay variations, the proposed method can provide an accurate estimation of segment delays. On average, 0.916 of correlation between estimated and sampled segment delays for a dozen of benchmarks.