考量多核系統下執行的模板應用程式利用動態資料搬移來消除記憶庫干擾

Dynamic Data Migration to Eliminate Bank-level Interference for Stencil Applications in Multicore Systems

陳衍昊(Yen-Hao Chen)

指導教授 ： 黃婷婷

國立清華大學/電機資訊學院/資訊工程學系/碩士(2014年)

https://doi.org/10.6843/NTHU.2014.00139

摘要

模板應用程式的特性是不斷地使用自身以及鄰近的點來進行相同的運算。新穎的自動轉換編譯技術可以有效率的產生磁磚式平行化模板應用程式。動態排成平行化模板應用程式大幅度的增加系統效能，然而，因為較少的閒置的核心以及較多的記憶體需求在一個時間被送至記憶體，造成了記憶體干擾問題惡化。傳統作業系統虛擬頁著色方法將記憶體虛擬頁分開來，但是沒辦法有效消除動態排成平行化模板應用程式的記憶體干擾。實驗結果顯示，與原本動態排成平行化模板應用程式相比，在八個核心、四個記憶庫的系統上面，我們的方法增快系統效能7%；在十六個核心、四個記憶庫的系統上面，則是增快9.3%。

關鍵字

動態排程 ； 模板應用程式 ； 記憶庫衝突 ； 記憶體干擾

並列摘要

A stencil computation repeatedly updates each point of a d-dimensional grid as a func-tion of itself and its near neighbors. Modern automatic transformation compiler framework can generate ecient tiling parallel stencil codes. Dynamically scheduling parallel stencils signicantly improves system performance. However, memory contention problem exacer-bates because of less idling cores and more memory requests sent to the DRAM memory in the same period of time. Traditional OS page coloring method which partitions the memory pages in advance can not alleviate the memory contention in dynamic scheduling parallel stencils. To address this issue, we provide a new software/hardware cooperation dynamic data migration method. Experimental evaluation in a 8-core x86 system shows that our method can improve the system performance by 7% as compared with dynamic scheduling stencils in 8-cores 4-memory banks system and by 9.3% in 16-cores 4 memory banks system.

並列關鍵字

dynamic scheduling ； stencils ； bank conflicts ； memory interference

參考文獻

Sadayappan, The Compiler-Assisted Dynamic Scheduling for Eective Parallelization

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Approach for Eliminating Bank-level Interference in Multicore Systems," PACT'12, pp.

367-376, 2012.

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