一個快速平行的移除共同路徑悲觀的方法

靜態時序分析在電路設計中是不可或缺的。為了考慮設計複雜度和因製造過程或環境因素所產生的變異，時序分析通常會使用‘最快/最慢’分離的方始來進行。這種方式能讓時序分析引擎考慮這些變異的影響。然而，這種方式的時序分析有時候會產生一些悲觀的情況，進而導致過於保守的設計。因此，在時序分析時需要透過共同路徑悲觀移除來消除。直觀的解法需要分析所有設計中的路徑，但在現在設計，邏輯閘的數量非常多，分析所有的路徑是不切實際的。在這篇論文中，我們提出一個新方法去有效的削減不必要的路徑和發展一個平行畫的引擎來快速且正確的移除共同路徑悲觀。實驗結果顯示我們的引擎比TAU 2014比賽第一名還要快且能維持100%的正確性。

關鍵字

時序分析；悲觀移除

並列摘要

Static timing analysis has always been indispensable in integrated circuit design. In order to consider design and electrical complexities (e.g., crosstalk coupling, voltage drops) as well as manufacturing and environmental variations, timing analysis is typically done using an “early-late” split. The early-late split timing analysis enables timers to effectively account for any within-chip variation effects. However, this dual-mode analysis may introduce unnecessary pessimism, which can lead to an over conservative design. Thus, common path pessimism removal (CPPR) is introduced to eliminate this pessimism during timing analysis. A naive approach would require the analysis of all paths in the design. For today’s designs with millions of gates, enumerating all paths is impractical. In this thesis, we propose a new approach to effectively prune the redundant paths and develop a multithreaded timing analysis tool called MTimer for fast and accurate CPPR. The results show that our timer can achieve 3.53X speedup comparing with the winner of the TAU 2014 contest and maintain 100% accuracy on removing common path pessimism during timing analysis.

並列關鍵字

timing analysis ； common path pessimism removal

參考文獻

[1] J. Bhasker and R. Chadha, Static timing analysis for nanometer designs: A practical

[2] J. Hu, D. Sinha and I. Keller “TAU 2014 contest on removing common path pessimism

[3] J. Zejda and P. Frain, “General framework for removal of clock network pessimism,”

2013 variation aware timing analysis contest,” in Proc. ISPD, pp. 171-178, 2013.

United States patent 5,636,372 (June 1997).

國際替代計量

一個快速平行的移除共同路徑悲觀的方法

主題瀏覽