調變閘極介電層及類磊晶矽薄膜通道厚度製作快速寫入/抹除之非揮發性記憶體

Fabrication of fast program/erase charge-trapping non-volatile memory using barrier-engineered dielectric and ultra-thin epi-like Si channel

吳思諭(Ssu-yu Wu)

指導教授 ： 吳孟奇 ； 楊智超

國立清華大學/電機資訊學院/電子工程研究所/碩士(2014年)

摘要

本論文以尖峰式雷射結晶(Pulse Laser Crystallization/green nanosecond laser spike annealing)技術，應用於非揮發性記憶體之主動層通道結晶製程，此高品質的多晶矽材料，可稱為“類磊晶矽”(epi-like Si)，並且可以使非晶矽薄膜轉換成具有1000 nm晶粒大小之類磊晶矽薄膜，同時利用化學機械研磨技術可將其表面平均粗糙度由37A降低為5A，可獲得具超薄(13 nm)平坦化之類磊晶矽薄膜通道，而以此低熱預算(< 450℃)特性結合金屬閘極，可成功開發出具有高效能之非揮發性記憶體，其次臨界擺幅可達170 mV/Decade以內以及開/關電流比可超過10^6。
此外，以感應耦合式電漿化學氣相沉積系統在低溫下製程(< 450℃)以及原子層沉積系統來沉積高介電值材料(Al2O3)，可沉積出低缺陷與高品質的介電層。並藉由能帶工程技術可成功的調變閘極介電層來製作氧化層/氮化層/(氧化鋁/)氧化層之金屬閘極非揮發性記憶體(VARIOT MONOS NVM)，並且使其性能與可靠度大幅提升，而操作電壓可以在7V與9V時，進行快速寫入(50 ns及100 ns)，而其記憶窗口分別為1.2V與1.9V，同時也具有優良的資料保持力，預估十年後電荷流失可維持在30%以內，另外，在元件耐久力方面，可以在經過1000次的重複寫入/抹除後，還具有良好的電性。因此能帶工程技術對於改善非揮發性記憶體的性能與可靠度效果非常優越，必為一個成功的改良技術。在未來，亦可發展成更複雜更有潛力的堆疊型非揮發性記憶體(Stacking Non-Volatile Memory)。

關鍵字

非揮發性記憶體 ； 能帶工程記憶體 ； 超薄類磊晶矽薄膜 ； 高介電常數材料

並列摘要

In this thesis, Pulse Laser Crystallization/green nanosecond laser spike annealing technique is applied to fabricate crystallized active layer channel, which consists of high quality poly-silicon material known as epi-like Si, of non-volatile memory (NVM). This technique turns amorphous silicon thin film into epi-like Si with 1000nm grain size, followed by CMP to reduce surface roughness from 37A to 5A, and ultra-thin (13nm) planarized epi-like silicon thin film channel is obtained. Due to the low thermal budget (< 450℃) of the process, when integrated with metal gate, high performance non-volatile memory can be developed with subthreshold swing below 170 mV/Decade and high on/off ratio beyond 10^6.
In addition, with inductively coupled plasma chemical vapor deposition system (ICPCVD) at low temperature process and depositing high-κ material (Al2O3) with ALD, low defect and high quality dielectric can be obtained. By applying barrier engineering technique to gate dielectric, metal gate NVM comprised of oxide / oxide / (Al2O3/) oxide is successfully demonstrated, abbreviated as VARIOT MONOS NVM, and thus performance and reliability is greatly improved. With program voltage at 7V and 9V, the device exhibits 1.2V and 1.9V memory window with 50ns and 100ns pulse width, respectively, and good data preservation of charge loss after 10 years is estimated to be within 30% as well. Besides, in terms of endurance, good electrical characteristic is retained after 1000 program/erase cycles. Therefore, barrier engineering technique having superiority in performance and reliability must be a successful modification technique, and can be developed into promising Stacking Non-Volatile Memory.

並列關鍵字

non-volatile memory ； barrier-engineered dielectric ； ultra-thin epi-like Si ； MONOS ； High-κ material

參考文獻

[1] Y.H. Lin , C.H. Chien et. al , "Low-Temperature Polycrystalline Silicon Thin-Film Flash Memory With Hafnium Silicate, " IEEE Transaction on Electron Devices, Vol. 54, No. 3, March 2007.

[2] H.S. a. R. Swann, "Chemical vapour deposition promoted by rf discharge," Solid-State Electronics, vol. 8, pp. 653-654, 1965.

[3] R. Chittick, "The preparation and properties of amorphous silicon," Journal of the Electrochemical Society, Vol. 116, p. 77, 1969.

[4] R.E.I. Schropp and M. Zeman, "Amorphous and Microcrystalline Solar Cells: Modeling, Materials, and Device Technology,"Kluwer Academic Publishers, 1998.

[5] W. G. Hawkins, “Polycrystalline-Silicon Device Technology for Large-Area Electronics,” IEEE Transaction on Electron Devices, Vol. ED-33, No. 4, pp. 477-481, April 1986.