內建自我測試電路應用於晶片內網路

A BIST Implementation for Network on a Chip

駱懷瑄(Huai-Syuan Luo)

指導教授 ： 劉靖家

國立清華大學/電機資訊學院/電機工程學系/碩士(2014年)

摘要

在此文中，我們實踐了對晶片內電路(network-on-chip)加上內建自我測試電路(BIST)方法並做測試。此方法使用了轉換延遲錯誤模型(transition fault model)和TG2(Transaction Generator 2)中的二維網絡模型。將內建自我測試電路產生的測試樣本測試晶片內電路的處理單元，且利用晶片內電路的內建交換機傳遞包裹(Packages)至其他晶片內電路中的處理單元做測試。此內建自我測試電路對晶片內電路中的處理單元一起分享測試樣本產生器(Test Pattern Generator)和多輸入特徵寄存器(Multiple-Input Signature Register)。每個處理單元有自己的測試控制器(Test Controller)會連到中央測試控制器(Central Test Controller)。由中央測試控制器下達命令至每個處理單元自己的測試控制器以決定每個處理單元的動作，像是對某個處理單元傳遞資料做內建自我測試。而我們最主要的目標就是減少內建自我測試電路的面積和增進整個內建自我測試電路的效能以提高錯誤涵蓋率(Fault coverage)。

關鍵字

內建自我測試電路 ； 晶片內網路

並列摘要

In this thesis, we present a built-in self-test methodology for testing the network-on-chip (NoC). This methodology uses transition fault model. And the NoC model is a 2-dimensional mesh which is TG2 benchmark. The proposed method is using BIST to generate test patterns to test processing element. And utilize inter-switch to send packets to test other processing element in NoC communication infrastructure. And this BIST design is sharing test pattern generator (TPG) and multiple-input signature register (MISR) for all processing elements. Every processing element has a test controller, all of these test controller chain together, and connect to the central test controller. Control signals sending to which processing element and the action of processing element will be decided by the central test controller, such as assign which router to test circuit. Our propose target is to decrease area overhead and improve performance for this BIST architecture.

並列關鍵字

Built-in self-test ； Network on Chip

參考文獻

[1] C.E Stroud, A Designer’s Guide to Build-in Self-Test. Kluwer Academic

publishers, Boston, 2002.

[5] N. Z. Basturkmen, S. M. Reddy, and J. Rajski, “Improved algorithms for constructive multi-phase test point insertion for scan based BIST”, in Proceedings of Design Automation Conference in Asia and South Pacific, 2002, pp. 604–611.

Conference, 1999.

[7] C.-A. Chen and S. Gupta, “Design of efficient BIST test pattern generators for delay testing”, IEEE Transactions on Computer-Aided Design of Integrated Circuits