- 學位論文
一個離散時間二階前饋三角積分類比數位轉換器
A Discrete Time Second Order Feed-Forward Delta Sigma Analog-to- Digital Converter
摘要
中文摘要 研究所別:電機工程學系 論文名稱: 一個離散時間二階前饋三角積分類比數位轉換器 指導教授:朱大舜 博士 研究生:101061569,謝乙豪 隨著科技的進步，製程日漸更新，在同樣的面積下能夠設計的電路也越來越多，效能也越來越好。也因為這樣的科技進步，許多人願意嘗試進行將大系統整合在一塊晶片的設計方式，而若是要將系統處理過的訊號放進電腦進行分析處理，則必須要使用類比數位轉換器，因此類比數位轉換器為大自然世界與數位電腦之間不可或缺的橋樑，又隨著醫學快速的發展對於生理訊號量測需求逐漸提高。本論文設計一個取樣頻率10MHz，訊號頻寬20kHz，超取樣率(OSR)為256的二階前饋三角積分類比數位轉換器，主要應用在生醫感測。透過交換式電容(Switch Capacitor)電路實現離散時間系統的三角積分類比數位轉換器，在設計上受到時脈抖動(Clock Jitter)和額外延遲(Excess Loop Delay)的影響較小但是在放大器的增益頻寬乘積的要求卻較高，因此在對低速應用上能設計出解析度較高的系統。整體的架構中包含了放大器、比較器、類比開關……等等。透過各種非理想效應的影響並加入進去系統模擬，例如，時脈饋穿(Clock Feedthrough)、時脈抖動(Clock Jitter)、放大器有限增益(Gain)、放大器有限增益頻寬積(Gain Bandwidth Product)、KT/C……等等，經由這些考慮可以先制定出放大器的規格，另外架構的選擇選用Full Feed-forward低失真架構大幅降低整體系統對放大器的規格要求並漸少積分器飽和所造成的失真。本論文採用TSMC 0.18um CMOS標準製程進行設計，並以Cadence Spectre軟體進行電路模擬。最後利用Full-Customer設計的技術來實踐整體電路，實際電路操作電壓在1.8V，訊號頻寬20kHz，訊號雜訊比SNR>95dB，有效位元達到15bit以上，整體平均功率消耗為3.06mW，效能指標(FoM)為1.06pJ/conv.，整體布局面積0.7x0.67〖 mm〗^2
並列摘要
Abstract(英文摘要) As technology advances, the process gradually updates, more and more circuits can be design in the same area, and the performance is getting better and better. With this scientific and technological progress, many people are willing to try to carry out large-scale system integrated in one chip design, but if they want to put the signal into a computer for analysis and processing, they must use the analog to digital converter. So analog to digital converter is the essential bridge between nature world and digital world. Due to the rapid development of medical technology, the requirement of the physiological signal measurement promote gradually. In this thesis, a sampling frequency of 10MHz, the signal bandwidth of 20kHz, and oversampling ratio (OSR) for 256 of the second-order delta-sigma analog-to digital converters, mainly used in biomedical sensing. The discrete-time system of Delta Sigma analog to digital converter is implemented by switch capacitor circuit. The affect by the clock jitter and additional delay (Excess Loop Delay) is small, but the gain bandwidth requirement of the amplifier is higher. So the high-resolution system can be designed for the low-speed application. The whole architecture includes amplifiers, comparator, analog switches ...... and so on. Add many kinds of non-ideal effects into the system to simulate like Clock Feedthrough, Clock Jitter , Finite Gain , Limited Gain bandwidth Product, Thermal noise...... and so on to formulate the amplifier specification. And then the choice of this work, Full Feed -forward low distortion structure, significantly reduces overall system amplifier specifications and the distortion of the integrator overload. This paper uses a standard TSMC 0.18um CMOS process design, and Cadence Spectre software for circuit simulation. Finally the technique of Full- Customer design implement the whole circuit. The circuit operating voltage at 1.8V, signal bandwidth 20kHz, signal to noise ratio SNR> 95dB, effective number of bits reach more than 15bits , the overall average power consumption is 3.06mW, the figure of merit (FoM) is 1.06 pJ/conv. and the total Layout area is 0.7x0.67〖 mm〗^2