- 學位論文
可參數化路由器管線架構和仲裁機制的晶片內網路架構動態時序模擬
Dynamic Timing Simulation for Network-on-Chip with Parameterized Router Pipeline Architectures and Arbitration Policies
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摘要
在之前我們提出了一個晶片內網路架構靜態時序模擬器，這個模擬器可以快速且精確的計算出每一個封包到達目的地所需要的時間，並支援模擬蟲洞傳輸、廣域非同步區域同步和動態電壓頻率調變。但是這個模擬器受限於靜態模擬，必須在模擬前就預先決定好所有封包進入晶片內網路架構的時間。另外模擬時間會隨著封包數量上升而呈現非線性增長，因為其必須掃描所有封包以確保較後進來的封包不會影響到前面的計算。 在這篇論文中，我們首先將此模擬器擴展至支援動態時序模擬，利用窗口技術偵測並修復基於較後進來封包所造成的錯誤。在此同時，我們提升模擬效能使其在大筆工作量底下有顯著提升。並且擴充模擬器使其支援大部分重要的晶片內網路架構設計參數，包括可參數化路由器管線架構和仲裁機制。最後，我們透過SystemC TLM-2.0介面將此晶片內網路架構動態時序模擬器與其他IP作模擬整合。 我們的晶片內網路架構動態時序模擬器所計算出來的時間結果會和從Arteris NoC compiler產生的時脈精確模型做驗證，驗證結果顯示所有的時間都完全符合從上述模型產生的封包波形。在得到精確結果的同時，此晶片內網路架構動態時序模擬器所需要的模擬時間相對於時脈精確模型有顯著的效能提升。作為參考，晶片內網路架構動態時序模擬器對於一個基於週期且在蟲洞傳輸底下會產生誤差的SystemC TG2晶片內網路架構模型有兩倍的加速。相對於其他精確模型，晶片內網路架構動態時序模擬器對於靜態模擬器有四倍加速，對於Arteris時脈精確模型則有188倍加速。
並列摘要
Previously, a fast and accurate static NoC timing simulator was proposed to calculate packet-arrival times. It can support different models of worm-hole switching, Global Asynchronous Local Synchronous (GALS) schemes, and Dynamic Voltage and Frequency Scaling (DVFS). However, the NoC simulator is limited to static simulation, i.e., packet injection times were known before simulation starts. Besides, the simulation time grows more than linearly as the number of injected packets increases, because the implementation scan all previous packets to make sure later packets do not interfere previous calculations. In this thesis, we first adapt the NoC timing simulator to support dynamic simulation, which use a windowing technique to detect and recovery the timing errors caused by newly-injected packets. In the mean time, we improve the performance of simulation significantly under large workloads. Also, we extend our NoC timing simulator to support most of the important NoC design parameters, including router pipeline architectures and several arbitration policies. Lastly, we wrap the simulator with SystemC TLM-2.0 (IEEE 1666) sockets for modeling compatibility with other IPs. The results of the proposed simulator are verified with NoC implementations (cycle-accurate RTL-level) created by a NoC compiler from Arteris. All timing results match perfectly with packet waveforms generated by above NoCs. We also achieve significant speed up when comparing with existing NoC simulators. As a reference, the simulator is about 2 times faster than a TG2 NoC model, which is a SystemC and cycle-based model without timing accuracy (due to worm-hole traffics). For other accurate models, the proposed dynamic simulator is 4 times faster than the static version, and about 188 times faster than a Arteris cycle-accurate model.
參考文獻
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