使用鰭式場效應電晶體之靜態隨機存取記憶體的缺陷模型分析與診斷方法

Defect Modeling, Analysis and Diagnosis for FinFET-Based SRAM

吳宗軒(Tsung-Hsuan Wu)

指導教授 ： 吳誠文

國立清華大學/電機資訊學院/電機工程學系/碩士(2014年)

摘要

近年來隨著元件的微縮、產生許多很難解決的問題，例如短通道效應和高漏電流。為了解決這些問題，改變元件的材料與結構便成了趨勢，而鰭式場效應電晶體則為一種解決方案。鰭式場效應電晶體的極薄基體通常是輕微摻雜，可以減少隨機摻雜擾動效應造成的臨界電壓漂移問題。因此使用鰭式場效應電晶體之靜態隨機存取記憶體將會擁有良好的穩定度和較低的功率消耗。鰭式場效應電晶體擁有自己獨特的缺陷模型基於鰭這種特別的結構。若在製造鰭的過程中有缺陷，有可能導致許多的電晶體損壞。因為根據電路設計布局，鰭有可會被許多電晶體使用。針對這類型的缺陷，我們提出一些準則，幫助我們可以直接從電路圖上找出哪些電晶體使用有缺陷的鰭而同時損壞的，並研究其可能對應的錯誤模型。在實驗中，我們發現有一些小缺陷並不會造成錯誤的邏輯行為，卻會造成可靠度下降。針對這類型的缺陷，我們進一步提出測試方法。為了改進缺陷水平，我們提出一種擁有相當高診斷能力的測試計畫，並且藉由讀取電流感應器的幫助，我們可以根據其測試結果，準確的找出對應的缺陷。而當鰭式場效應電晶體之靜態隨機存取記憶體發生錯誤時，我們會事先建立一個對應表來幫助我們快速找出是哪一種缺陷造成錯誤。在本篇論文，我們針對記憶體細胞中的每個電晶體注入缺陷，並產生可模擬的測試電路。而提出的測試方法在以積體電路為重點的模擬程式裡被驗證過，而程式使用的鰭式場效應電晶體模擬模型是依據PTM網站提供的20奈米低待機功率模型。

關鍵字

記憶體測試 ； 鰭式場效應電晶體 ； 錯誤模型 ； 失效分析 ； 瑕疵診斷

並列摘要

FinFET is a solution to the process-scaling problems, such as short channel effect and large leakage. The thin body of FinFET is typically lightly doped, thereby eliminating the threshold voltage deviation caused by random dopant fluctuation effects. The FinFET-based SRAM, therefore, has high stability and low power consumption. However, FinFET has its specific defect models due to the special fin structure. The defects occurred on nanowire could affect fins of multiple transistors according to FinFET-specific layouts. Targeting these defects, we propose some criteria to investigate defect candidates from schematics, then simulating and summarizing the corresponding fault models. In our summary, there are special defects, vague defects, causing no logical fault but leading to reliability degradation, especially in deep sub-micron technology. Focusing on vague defects, we further propose a method to test them. In order to improve defect level, we propose a testing strategy that achieves high diagnosis resolution to identify these defect candidates with read current sensor support. A defect dictionary is finally built by this method, assisting in fast defect diagnosis for the FinFET-based SRAM in the future. In this thesis, we inject these defects respectively to each transistor in FinFET-based 6T-SRAM circuits for simulation. The testing strategy has been validated by SPICE simulation using 20 nm low-standby power (LSTP) model cards from the PTM website (Predictive Technology Model).

並列關鍵字

memory test ； FinFET ； fault model ； failure analysis ； defect diagnosis

參考文獻

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