利用空閒功能單元以最大化浮水印數量之方法研究

Utilizing Idle Functional Units for Maximizng The Number of IP Watermarks

林琮棠(Tsung-Tang Lin)

指導教授 ： 黃世旭

中原大學/電機資訊學院/電子工程研究所/碩士(2015年)

摘要

隨著晶片系統設計變的龐大，設計負責特定功能且可重用的矽智財(Intellectual Property Cores)產品來加速晶片設計的生意逐漸增加，但伴隨矽智財的商機增長，盜取矽智財的案例也逐漸上升，因此在矽智財保護的設計研究中使用浮水印(watermarks)阻止矽智財被竊取是一件很重要的問題。先前的研究顯示，增加浮水印的個數可以使矽智財保護的安全性以及差異性提高。且在高階合成階段利用矽智財輸出端暫時關閉的時間(Temporally Free)設計浮水印已經被提出作為有效且低額外設計消耗的方法，透過研究此設計方法的過程中，我們發現可以利用高階合成中的空閒功能單元(Idle Functional Units)進一步的增加浮水印的個數。在本篇文章中，我們提出在高階合成階段利用空閒功能單元最大化浮水印數量的設計方法，我們的方法是以啟發式(Heuristic)演算法方法在額外資源的設計條件考量下，利用空閒功能單元將浮水印的數量最大化，比起既有的浮水印設計研究，我們可以達到更多的浮水印數量，並且不會產生過多的額外資源負擔。

關鍵字

高階合成 ； 浮水印最大化 ； 矽智財保護 ； 空閒功能單元

並列摘要

To cope with the increasing design complexity, the companies reuse more and more intellectual property cores to accelerate integrated circuit design. As the number of intellectual properties core is growing, the cases of intellectual property core theft are also on the rise. The protection of intellectual property core by inserting watermarks during the integrated circuit design is a very important issue.
Previous works have shown that more number of intellectual property watermarks can let intellectual property cores to achieve high security and difference. In the high-level synthesis process, to utilize the temporally free output slots (in the operating stage) to produce watermarks is recognized as a useful technique for protecting intellectual property cores. In this thesis, we point out that the utilization of the idle functional units can increase the number of watermarks. Based on this observation, we propose an effective approach to increase the number of watermarking technique based on the utilization of idle functional units in the high level synthesis process. Our objective is to maximize the number of watermarks under the overhead constraint. Experimental results show that our approach achieves very good results.

並列關鍵字

High-Level Synthesis ； IP Watermarks ； IP Protection ； Idle Functional Units

參考文獻

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