- 學位論文
晶片變異感知頂層時鐘樹合成方法研究
On-Chip-Variation-Aware Top-Level Clock Tree Synthesis Methodology
摘要
隨著科技的進步，元件尺寸越來越小，單一晶片上所包含元件的數量大幅上升，對先進製程而言，製程變異(On-Chip-Variation)所帶來的影響越發的嚴重，尤其在進行時鐘樹合成的時候，可能因為時序上些微的差異對整個晶片造成極大的影響，所以如何有效的降低時鐘樹的製程變異(On-Chip-Variation)是急需解決的一個問題。 現今的晶片設計上，系統晶片(System-on-Chip)都是由許多獨立的區塊組成的，區塊與區塊之間的頂層時鐘樹因為元件之間的距離較遠極度容易受到製成變異的影響，所以如果能夠有效的降低頂層時鐘樹的製程變異(On-Chip Variation)，就能夠進而控制整個晶片上各個模組受到製程變異(On-Chip Variation)所帶來的影響。 在本篇論文中，我們基於上述的觀察，針對頂層時鐘樹，提出一個設計流程，與業界的工具程式做結合，首先，分析使用業界工具合成出來原始的時鐘樹，之後利用我們提出的演算法，重新給定時鐘樹上每個元件位置，並重新帶回工具程式做時鐘樹合成，經過我們的優化，最後得到一個大幅降低製程變異的頂層時鐘樹。
並列摘要
As the process technology continues to shrink, the size of a standard cell is smaller. Thus, the design complexity is higher. Moreover, the influence of on-chip variation also becomes more serious. Especially, in the clock tree synthesis, a small timing variation may make a big impact on the chip. Therefore, the reduction of the on-chip variation of clock tree is an important topic for the industry. A system-on-chip design consists of a lot of blocks. Top-level clock tree among blocks is much easier influenced by on-chip variation because the distance between blocks is longer. If we can reduce on-chip variation of top-level clock tree effectively, the on-chip variation of the whole chip is easier to control. Base on this observation, in this thesis, we propose a design flow, which can be integrated with existing APR Tools, for top-level clock tree design. The proposed design flow is below. First, we analyze the original clock tree which is synthesized by APR Tools. Then, we develop an algorithm to find the new location of each clock buffer and guide the APR tool to resynthesize the top-level clock tree. Experimental results show that, after our optimization, we can obtain a top-level clock tree with a significantly reduced on-chip variation