採用機器學習建構與評估巨集擺置的可繞線性方法探討

Study on Machine Learning Techniques for Building and Evaluation of Routability-driven Macro Placement

吳至軒(Chih-Shuan Wu)

指導教授 ： 鄭維凱

中原大學/電機資訊學院/資訊工程研究所/碩士(2018年)

https://doi.org/10.6840/cycu201800758

摘要

隨著超大型積體電路設計微縮技術的成熟，相同尺寸的晶片能容納的電路數量呈倍數成長且功能也日益強大，在22奈米製程設計的規則下，已將詳細繞線獨立成另一個步驟階段，然而實體設計階段，在放置階段的過程中忽略詳細繞線規則是可能直接導致設計失敗，同時此階段的成功與否必須等到繞線結束後才能得知，因此在放置階段事先評估可繞線性問題是實體設計階段中非常重要問題。
本論文提出了一個新穎的前處理方法以及一個特別的機器學習模型架構。採用前處理方法提取更多的特徵，透過我們預先加入的外部條件將Pin與Net的關係化簡成處理點與直線的連通關係，取代探討複雜的樹如何生長問題，藉此將事後評估壅塞的方式提前到事前評估，最後將其視一種新的特徵，接著再配合本論文研究中所定義的所有特徵，導入到我們建構的兩種不同的機器學習模型架構中進行分群探索與預測，進一步的找出特徵與特徵的潛在關係加以分析，制訂出回饋與微調的參考機制，透過這兩個機制的迭代輸出準確度較高的預測結果。
未來期望能將此方法整合至實體設計階段中，在放置階段作為參考的依據達到事先有效預測，避免在詳細繞線階段發生不可行設計的結果。

關鍵字

實體設計 ； 擺置 ； 放置 ； 繞線 ； 可繞線性 ； 機器學習 ； 晶片設計後段

並列摘要

In current very-large-scale-integration design miniature technology, the number of circuits in the same chip size is increasing and the performance is more powerful. To follow the rules of the 22nm process design, global routing and detailed routing are separated into two design steps. However, in the physical design stage, ignoring detailed routing rules during the placement stage may directly lead to design failure. At the same time, to make sure the success of physical design must only after the end of routing stage, so pre-evaluating the routability during the placement stage is a very important issue in the physical design stage.
This paper proposes a novel pre-processing method and a special machine learning model architecture. By extracting more features using pre-processing, we add external conditions that can simplify the relationship of connections between pin and net. Instead of discussing how to grow up the tree, we move the evaluation of congestion to the pre-assessment stage and define it, then push all the feature of our study to machine learning architecture that build from two different model. The model will find out the potential relationship between features and features, and we can build the mechanism for feedback and modify, that can get the best prediction results.
In the future, we will integrate our method into the physical design flow; help the placement stage to avoid the fail in the routing stage.

並列關鍵字

Physical design ； placement ； routing ； Routability-driven ； machine learning ； IC design

參考文獻

[1]Stephen M. (Steve) Trimberger, “Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology”, EEE Solid-State Circuits Magazine, Volume: 10, Issue: 2, pp.16-29, Spring 2018.

[2]Nankang IC Design Incubation Center, “Physical Design Flow”, 2012.

[3]Amir H. Salek, Jinan Lou, and Massoud Pedram, “An integrated logical and physical design flow for deep submicron circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 18, Issue 9, Sep 1999.

[4]Yi-F. Chen, C-C. Huang, C-H. Chiou, Y-W. Chang and C-J. Wang, Routability-Driven Blockage-Aware Macro Placement”, 51st ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1-6, 2014.

[5]Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, and Kai-Yuan Chao, “NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing with Bounded-Length Maze Routing”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 32, Issue: 5, pp.709-722, May 2013.