本研究探討以基於差動對架構之非揮發性記憶體(non-volatile memory, NVM),實現應用於人工神經網路(artificial neural network, ANN)電路的突觸權元件。首先提出以一對非重疊離子佈值(non-overlapped implantation,NOI)電晶體設計出具非揮發性儲存能力的差動對突觸元件。NOI差動對突觸元件屬於非揮發性類比記憶體,不同於以往的NOI單電晶體突觸元件,本研究設計的差動對突觸可儲存正突觸權重或負突觸權重兩種資料。 目前已有許多神經形態(Neuromorphic)系統之研究被發表,神經形態電路可實現分散式平行運算,因為權重儲存與計算都是透過突觸元件來執行。而NOI差動對是非常有淺力的突觸元件,因為能夠在本地(local)執行權重存儲與計算,還可透過可儲存正、負突觸權重的特色改善乘法運算的線性度。 本研究首次提出以NOI差動對突觸元件設計出包含3個神經元、36個突觸的類神經網路,並以使用IRIS數據集作基準來驗證類神經網路在訓練與測試之表現透過matlab模擬,NOI差動對類神經網路在訓練與辨識結果皆優於NOI單電晶體類神經網路,最後以0.25微米CMOS製程製作出NOI差動對類神經晶片,通過chip-in-the-loop訓練流程,對硬體晶片做訓練,實驗的結果顯示NOI差動對突觸元 件之設計不僅克服了NOI單電晶體突觸僅能儲存正突觸權重的限制,同時以NOI差動對突觸元件設計的類神經網路具有更好的辨識能力。根據矽晶片的實驗結果可推斷NOI差動對類神經網路可藉由擴展NOI差動對陣列來處理更大量、更複雜的數據集。
A non-volatile memory (NVM) realization of the synaptic weight for an artificial neural network (ANN) circuit is investigated. Two non-overlapped implantation (NOI) nMOSFETs are used to form a NVM differential pair as an artificial synapse. The pair of NOI transistors are non-volatile analog memories and capable of storing positive or negative synaptic weight. The NOI differential pair is able to perform weight storage and computing locally, and improve the multiplicative function for the positive and negative synaptic weight functions. In this work, a NOI differential pair based silicon neural chip of three neurons with 36 analog synapses is designed, simulated, fabricated, and verified by the chip-in-the-loop learning process. The classification performance of the neural chip when training and testing with the IRIS dataset is reported. This differential pair design not only overcomes the potential constraint in the weights of NOI but also exhibits better classification performances than that of single NOI-based ANN.