透過您的圖書館登入
IP:3.141.197.212
  • 學位論文

具邊界限制模組之定形配置設計

Slicing Floorplan Design with Boundary-Constrained Modules

指導教授 : 王廷基
若您是本文的作者,可授權文章由華藝線上圖書館中協助推廣。

摘要


在本篇論文中,我們討論具邊界限制模組之定形配置設計(slicing floorplan design)。我們設計一個時間複雜度為平方項的方法,此方法可以正確地將一定形配置設計轉換成另一符合所有邊界限制之定形配置設計。這個轉換的方法被整合到模擬退火(simulated annealing process)的方法中,以試著求得一個最佳的解。不像其他已存在的演算法,例如在[10]被提出的演算法,我們所提出的定形配置演算法可以永遠產生出符合邊界限制的解,相對於在[10]所提出的演算法,這是我們的演算法最主要的優點。 我們的演算法已以C語言實現,並利用兩個MCNC的電路: ami33及ami49,做實驗。當只考慮面積的最佳化時,我們的演算法針對ami33及ami49可改進在[10]所提出的演算法達9.38%及2.97%。同時針對ami33及ami49,繞線長度也被我們的演算法改進達6.9%及15.64%。當同時考慮面積與繞線長度的最佳化時,針對ami33及ami49,我們的演算法可改進面積達4.88%及4.48%,可改進繞線長度達8.53%及10.87%。在運算時間方面,我們的演算法幾乎在所有的測試例子中都只花不到一分鐘。

並列摘要


We consider in this thesis the problem of slicing floorplan design with boundary-constrained modules. We develop a quadratic-time method that correctly transform a slicing floorplan into one that satisfies all given boundary constraints. This transformation method is then incorporated into a simulated annealing process to seek for a best possible solution. Unlike any other existing algorithm such as the one in [10], our floorplanning algorithm is always able to generate solutions satisfying all given boundary constraints, which is the major advantage of our algorithm over the algorithm in [10]. Our algorithm has been implemented in C language, and tested on two MCNC examples: ami33, ami49. When optimizing the area alone, our algorithm improved the average area up to 9.38% and 2.97% for ami33 and ami49, respectively, over the algorithm in [10]. Meanwhile the average interconnect wirelength was also improved by our algorithm up to 6.9% and 15.64% for ami33 and for ami49, respectively. When optimizing both area and interconnect wirelength, our algorithm was able to improve the average area up to 4.88% for ami33, 4.48% for ami49, and to improve the average wirelength up to 8.53% for ami33, 10.87% for ami49. As for the run time, our algorithm took less than one minute for almost all test cases.

參考文獻


[1] P.-N. Guo, C.-K. Cheng and T. Yoshimura, “An O-Tree Representation of Non-Slicing Floorplan and Its Applications,” Proc. Design Automation Conf., 1999, pp. 268-273.
[2] H. Murata and E. S. Kuh, “Sequence-Pair Based Placement Method for Hard/Soft/Pre-Placed Modules,” Proc. International symposium on Physical Design, 1998, 167-172.
[3] R. H. J. M. Otten, “Automatic Floorplan Design,” Proc. Design Automation Conference, 1982, pp. 261-267.
[4] R. H. J. M. Otten, “Efficient Floorplan Optimization,” Proc. International Conference on Computer Design, 1983, pp. 499-502.
[5] L. Stockmeyer, “Optimal Orientations of Cells in Slicing Floorplan Designs,” Information and Control, 1983, pp. 91-101.

延伸閱讀