八位元低電壓雙區間式類比數位轉換器之設計與實現

Design and Implementation of An 8-bit Low-Voltage Subranging Analog-to-Digital Converter

鄭又文(Yu_Wen Cheng)

指導教授 ： 鍾文耀

中原大學/工學院/電子工程研究所/碩士(2001年)

https://doi.org/10.6840/cycu200100279

摘要

本論文描述一八位元低電壓雙區間式類比至數位轉換器(8-bit Low-Voltage Subranging Analog-to-Digital Converter) 之設計與實現。此架構為雙區間式類比數位轉換器，主要架構可分為三個部分:第一級的約略類比數位轉換電路(Coarse ADC)、第二級的精密類比數位轉換電路(Fine ADC)及類比數位轉換器結合減法器單元。
此類比數位轉換器中採用數位至類比轉換器結合減法器(combined DAC/subtraction)的技術來縮短操作時間和晶片面積，並選擇兩級CMOS 斷路式比較器(chopper-type comparators)以獲得較小的消耗功率及較小的佈局面積。電路由比較器、數位編碼器、減法器、參考電壓產生器等數個子電路所組合而成。
論文所設計之轉換器採用聯華積體電路製造公司 (UMC) 0.5μm DPDM CMOS製程來實現，晶片佈局面積為936μm × 600μm。轉換器的輸入操作範圍為0 至3.3V，於操作電壓3.3V及轉換速度3MHz下，消耗功率為39.8mW。

關鍵字

比較器 ； 雙區間式 ； 轉換器

並列摘要

This thesis describes the design and implementation of an 8-bit low voltage subranging analog-to-digital converter. The technique of combined DAC/subtraction is used to reduce the operation time and area. Furthermore, in order to achieve the goal of high-speed operation, lower power consumption and compact chip area, chopper-type CMOS comparators are adopted.
The chip has been implemented by using UMC 0.5μm DPDM CMOS process and the layout area is 936μm × 600μm. The A/D converter can operate at 3MHz with a single 3.3V power supply and the input range is 0V to 3.3V and power dissipation is 39.8mW.

並列關鍵字

converter ； subranging ； comparator

參考文獻

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