- 學位論文
高速模糊推論處理器之設計與研究
A Study on the Hardware Design of High Speed Fuzzy Inference Processor
摘要
在這篇論文中，我們探討適合類梯形歸屬函數之即時應用的高速模糊推論處理器設計。我們的研究分為以下兩個部份: (1)在第一顆晶片的架構中，我們主要是提出一個有效率的類梯形歸屬函數表示法，並因此對於極大—極小值運算分析導出一些特性，而能夠快速得到歸屬度，所以在我們的處理器中並不需要轉換離散集合中歸屬函數所有的元素。也因此我們可以成功提升模糊推論的速度 (2) 在第二顆晶片，我們提出一個節省晶片面積的新架構。以往的架構為了提昇推論速度都大量的使用平行運算，但是平行運算需要較多的硬體需求。事實上，對大部份的模糊系統而言，對於模糊推論的結果有貢獻的規則其實只是所有規則中的一小部份。我們新架構主要的特色包括:一個分析單元來判斷規則是否動作，一個排序單元每次在模糊判斷前安排四條有動作的規則，使用記憶體單元來儲存規則庫。由於這個架構可以刪除不動作的規則，所以使用的硬體資源也較少。 我們使用TSMC 0.35 μm的製程來實現這兩顆晶片。根據我們分析的結果可知工作頻率皆可達60MHz。與其他架構比較，由實驗結果可知我們的架構可以達到較好的表現。
並列摘要
In this thesis, we will study the design of high-speed VLSI fuzzy inference processor using trapezoid-shaped membership functions for the real-time applications. Our research includes the following two parts: (1) The main distinction of the first chip is that it may obtain the matching degree very fast because it needs not to traverse all the elements in the universe disclosure set. The speedup is achieved by an effective format for trapezoid-shaped membership functions and an interesting property derived by a careful analysis to the conditions of max-min calculation. (2) The main distinction of the second chip is that it may save a lot of chip area. Previous architectures for high performance are to exploit the temporal parallelism and spatial parallelism inherited in fuzzy inference processing. However, applying fully parallelism to calculation may suffer from hardware costs. In fact, for most cases, the active rules, which make non-null contributions in fuzzy inference, is only a small part of the rules. Based on the basic idea, we implemented the second chip. The main features of the new architecture are: an analysis unit to identify the active rules, a scheduling unit to arrange four active rules for fuzzy decision at a time, and memory units to store the knowledge bases. The new architecture of fuzzy inference processor uses fewer hardware resources by discarding non-active rules. Both the two fuzzy inference processors have been implemented by using TSMC 0.35μm process as the target technology. According to our analysis, the working frequency of both chips achieves 60MHz. Compared with other existing hardware architectures, experimental data shows that the proposed approaches achieve higher performance.
參考文獻
延伸閱讀
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