根據美國半導體技術藍圖,西元2006年時Si MOSFET的閘極氧化層二氧化矽厚度將低於2nm,此時將因穿隧效應使閘極漏電流密度大於1A/cm2,使得元件無法操作,因此利用高介電係數材料替代二氧化矽作為閘極氧化層成為解決此問題的途徑。 Y2O3薄膜具有高介電常數(k~18)、低漏電流、不易與Si基板反應形成二氧化矽等特性,可應用在矽製程中電晶體的閘極氧化層與記憶體DRAM的介電層。 本實驗主旨在研究以稀土族氧化物Y2O3薄膜作為高介電係數材料的物性及電性之表現。利用射頻磁控濺鍍系統在p-type(100)之矽基板上沉積Y2O3薄膜,並製作MOS之電容結構以量測其介電特性,並針對Y2O3之漏電流密度及介電常數等與製程參數之關係加以研究探討。 本實驗中,以射頻磁控濺鍍方式成長之Y2O3薄膜在二氧化矽等效厚度為41Å到60.5Å時均低於5×10-7A/cm2漏電流密度,介電常數為8.02到14.9,在未經回火前其介面缺陷密度約1.3×1013cm-2eV-1,O2回火後介面缺陷密度約3.7×1011cm-2eV-1,初步證明Y2O3為具有潛力閘介電層,惟需再研究製程之最佳化,以去除於Si與Y2O3之間可能產生的介面層。
The area of advanced gate dielectrics has gained considerable attention recently because technology roadmaps predict the need for a sub-20Å SiO2 for next 10 years, and there are significant leakage current and reliability concerns for SiO2 in this regime. Therefore it’s an important issue to develop alternate high k materials as gate dielectrics to replace SiO2. Here we study and develop the process for Y2O3(ε~18), a rare earth oxide, on Si as gate dielectrics. The electrical and physical properties of the Y2O3 films grown by RF magnetron sputtering were studied. Y2O3 thin films showed that the MOS capacitor using Y2O3 dielectrics keep showed leakage current density less than 5×10-7 A/cm2 for EOT from 41Å to 60.5Å, and dielectric constant of 8.02 to 14.9. The interface density is 1.3×1013cm-2eV-1 before annealing and 3.7×1011cm-2eV-1 after O2 annealing. Our preliminary results showed that the Y2O3 is a potential candidate for the alteration Si MOSFET gate dielectrics. Yet the growth process needs to be optimized to eliminate the interface layer between Si and Y2O3.