本論文以複雜型可程式化邏輯晶片(Complex Programmable Logic Device, CPLD)之功能適當的設計應用於壓電陶瓷馬達驅動電路上,電路的實現採用階層式、模組化的設計方式,降低其複雜度,並以電路共用的概念,降低邏輯閘數量,達到最佳化實現的目的。此晶片將可達到高度運算速度,進而提高取樣頻率,減低微處理器計算負擔 ,同時降低高次諧波失真的問題。而由於集中數位元件於一晶片之中,零件老化問題較不 嚴重,且對溫度變化也不敏感,有利於系統長期運轉下維持精密伺服運轉功能,以提昇現階段使用類比式PWM可調變電壓型之驅動器的控制性能與機能;以達到數位化驅動器的目的。
This thesis presents, a digital circuitry is designed based on the use of CPLD for the driver of a piezoelectric ceramic motor. By using the hierarchical and modular realization strategy, the designed circuits can be re-used to reduce the design complexity and the total gate counts for optimum design. This designed chip will calculate at high speed to boost the sampling frequency and reduce the burden of DSP.At the same time, the high speed switching operation will decrease the problem of high harmonic distortion. Meanwhile , the function of this chip will maintain the accurate performance within long time operation to against the temperature variation. Via appropriate design, the driver is able to enhance the PWM control functions.