- 學位論文
低電壓電荷充電泵鎖相迴路於時脈產生器之設計研究
Research on the Design of Low Voltage Charge-Pump Phase Locked Loops for Clock Generator
摘要
本論文的主要目的在於設計一結合石英振盪器與電荷充電泵鎖相迴路之低電壓時脈產生器。系統中主要電路方塊是由相頻偵測器( Phase Frequency Detector , PFD)、電荷充電泵( Charge Pump , CP )、壓控振盪器(Voltage Controlled Oscillator , VCO )、迴路濾波器( Loop Filter , LF )、除頻器( Divider )及石英振盪器( Crystal Oscillator )所組成。 鎖相迴路利用到幾個電路:相頻偵測器是採用可消除死界( Dead-Zone )影響的nc-PFD架構來實現；並加入一修正電路，使相頻偵測器輸出不會有UP與Down ( DN )信號同時上升的情況，壓控振盪器則是利用具有雙延遲路徑的四級環型振盪器( ring oscillator with dual-delay path )，每一級皆使用差動放大器以降低雜訊的干擾，並使用一個二階之濾波器將相頻偵測器與電荷充電泵輸出端的高頻雜訊濾除，以降低控制電壓上的擾動。在石英振盪器部分，採用Pierce架構的振盪器，提供一個穩定的16.62MHz輸入信號源。 本論文採用台灣積體電路製造公司( TSMC ) 之0.35μm 1P4M 製程來實現，石英振盪器的佈局面積為370x430μm2，適用於16MHz~25MHz的石英振盪子( Crystal Resonator )，鎖相迴路佈局面積為400x650 μm2，由石英振盪器提供一個16.62MHz給鎖相迴路，系統的輸出為16.62MHz、33.24MHz及66.48MHz三個頻率，壓控環型振盪器最大頻率為590MHz，經量測後，鎖相迴路輸出抖動在輸出16.62MHz時為270ps，供應電壓為3V。
並列摘要
The aim of this thesis is to design a low voltage charge pump phase locked loop ( CP-PLL ) for clock generator applications. The core circuit blocks of the system consist of a phase frequency detector, charge pump, voltage controlled oscillator, loop filter, divider and crystal oscillator. PLLs contain several circuits: First, the frame of nc-PFD is used to eliminate the dead-zone in the PLL. With an added modified circuit, the proposed PFD overcomes the disadvantage of nc-PFD. The outputs UP and down ( DN ) will never rise at the same time. Second, the VCO is based on a four stages ring oscillator where each stage is a voltage controlled differential delay cell with dual delay paths. The VCO prevents the jitter noise from the power line and substrate. Finally, we use the second order loop filter to decrease the influence of voltage step and filter out the higher frequency noise from phase frequency detector and charge pump. A Pierce crystal oscillator is implemented in the system, which providing a stable 16.62MHz signal to the PLL. The chip has been implemented in the TSMC 0.35μm 1P4M CMOS technology and the layout area of the crystal oscillator is 370x430μm2. The crystal oscillator can be used at resonating frequencies of 16~25MHz. The layout area of the PLL is 400 x 650μm2. For 3V power supply, the input frequency is 16.62MHz that provides by crystal oscillator, and the output frequencies are 16.62MHz, 33.24MHz, and 66.48MHz. The jitter of the output was approximate 270ps at 16.62MHz. The proposed PLL can be used in clock generator and frequency synthesizer applications.