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  • 學位論文

以類神經網路分析微影覆蓋幾何誤差

Geometric Analysis of Photolithography Overlay Error Using Neural Networks

指導教授 : 張耀仁
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摘要


在IC製造過程中,微影是最關鍵的製程之一,直接關係著最小特徵尺寸的極限,對準與曝光則是微影製程中最重要的技術,在曝光過程中因為受到步進機本身、晶圓狀況以及外在環境的影響,會造成層間IC電路設計圖案疊合時發生位移,稱為覆蓋誤差,超過容忍度的覆蓋誤差會造成電路容易發生短路或斷路,降低產品良率。隨著晶圓尺寸的增加,特徵尺寸的縮小,覆蓋誤差的控制成為維持生產良率的關鍵,須以更可靠的方式來補償覆蓋誤差,類神經網路具備對未知非線性函數近似的能力,以類神經網路模擬由晶圓或環境所造成的誤差,並將之濾除,再配合最小平方法估測實際由步進機所造成的覆蓋誤差參數,如此可以避免因為受晶圓變形影響,對步進機做出錯誤的修正。 徑向基底網路具有快速學習的優點,因此用其作為函數近似網路以提高估測的時效性,結果顯示,混合式類神經網路估測具有過濾晶圓隨機誤差的效果,可針對步進機可調整之誤差項求得參數,以提供更可靠的分析結果,作為工程人員補償步進機覆蓋誤差時的重要參考。

並列摘要


Photolithography is the key process of IC manufacturing and directly influences the limit of critical dimension (CD). The alignment and exposure represents two major technologies in modern photolithography. During the exposure stage the circuit patterns between two conjunctive layers may cause displacement because of the influence of the stepper, wafer condition and external environment. This leads to overlay error. If the overlay error exceeds the limit of fault tolerance, the out outcome of short circuit will decrease the yield of products. With the increase of the wafer diameter and the shrinking of the feature size, the control of the overlay error becomes the key factor of maintaining the yield of products. Therefore, the overlay error should be compensated by a more reliable method. The neural network has the ability to approximate any unknown nonlinear function, which is to take advantage to filter the overlay error caused by the wafer or environment, and to estimate the parameters of overlay error model with the least-square method. Can be then avoided any wrong adjustments of the stepper due to the wafer distortion. Because the Radial Basis Function network has the property of rapid learning, it can be used as function-approximation to increase the efficiency of estimation. From the results, it is found that the hybrid neural network has the ability to filter out the random error of wafer and accurate parameters of overlay error model can be obtained.

參考文獻


Performance”, IEEE Control Systems Magazine October 2002.
4.C. K. Peski, “Minimizing Patter Registration Error Through Wafer Stepper
Detection of Higher Order Contributions to Misalignment”, SPIE Integrated
11.C. F. Chien, and K.H.Chang, “Modeling overlay errors and sampling
strategies to improve yield” Journal of the Chinese Institute of Industrial

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