- 學位論文
應用於超大型積體電路之多階層時序導向繞線方法
A Timing-Driven Multilevel Routing Algorithm for VLSI Design
摘要
隨著科技的進步，製程的技術亦進入了深次微米的時代，伴隨而產生的問題也越來越多。在一個超大型積體電路中，元件數已漸漸超出目前商業工具所能處理的數量，而電路連線對晶片效能的影響也越來越顯著。所以現在繞線所要考慮的問題不是只有可繞度一種，還需要考慮時序收斂以及降低雜訊等相關的問題。 本篇論文提出了一個時序導向之多階層繞線方法，其利用critical paths的資訊作為考量，優先處理critical path的繞線，並以多階層繞線方法為架構，將其餘的導線使用congestion driven global route與timing driven detailed route來完成繞線。跟以往的多階層繞線不一樣的地方在於，我們的多階層繞線只有一個階段，只做coarsen的動作，以縮短繞線的時間，並於coarsen階段時，反覆的處理無法繞線的導線，而不等到作uncoarsen才作處理。另外我們在處理critical path的繞線時，使用Elmore delay model的為基礎作繞線，以降低critical path上的時序延遲。 在實驗的結果中，我們可以看到在採用時序導向的時序延遲要比一般的繞線結果要好，改善範圍從20%~80%。此結果證明我們的以critical path為考量，的確可以降低critical path的時序延遲。在繞線完成度的部分，我們的benchmark的utilization大約為50%，繞線的完成度在99%以上。由此結果得知，我們在處理繞線完成度接近100%。在實驗流程的部分，我們使用實際的電路作為我們的實驗輸入，並且能夠跟現有的CAD設計流程作整合，讓本論文更具實用性。
並列摘要
As the process technology enters the deep sub-micron era, the side-effect is become more and more serious. The number of components in VLSI design is over the handing of current commercial tool and the circuit connection deep influence the chip performance. Now, routing problem not only consider routability but also timing convergence and reduce noise. This paper propose a timing driven multilevel routing method. We consider critical path give priority to route and use multilevel framework to route rest net by congestion driven global route and timing driven detailed route. The different with post multilevel routing is our multilevel routing only adopt coarsen stage. We use coarsen stage to reduce our routing search time and we process fail net in coarsen stage instead of uncoarsen stage. When we route critical path, we use elmore delay model as guide to reduce the timing delay at critical path. Experimental results show that our timing delay which adopt timing driven improve form 20% to 80% than normal multilevel routing. The results prove that we consider critical path can reduce the timing delay obviously. Our routability is over 99% in these test cases which row utilization is about 50%. In the experimental flow, we use the real circuit case as our input, and integrate with commercial CAD design flow.
參考文獻
延伸閱讀
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