- 學位論文
電路佈局製程轉換的時序最佳化方法
Timing Optimization Methodology for Physical Layout Migration
摘要
在一般的 Physical layout migration 工具中, 對於Physical layout 的處理, 是採取等比例與佈局設計規則的方式來對 layout 進行壓縮的處理, 這其中也包含了MOS 電晶體 (transistor) 的寬度 (width) 的處理方式, 對於這種方式所完成的 Physical layout migration, 雖然可以得到 100% DRC 正確的 (DRC clean) 結果, 但是對於電路的時序特性並沒有作任何的處理. 在本文中, 對於電路的時序特性藉由結合 Perl 直述式語言 (script language) 與市面上的商業化 EDA軟體, 並且整合成一個完整的設計流程, 提出了一個使用 Physical layout migration 工具為主體, 而使得Physical layout migration 的結果達到時序最佳化方法., 透過分析 SPICE 模型 (model) 與原始Physical layout design 的內容, 應用 Physical layout migration 工具來產生與一般傳統 Physical layout migration 方法的不同結果, 在實驗結果上, 使用本文方法所得到的結果可以比一般傳統 Physical layout migration 方法所產生的結果, 在時序上可以達到最高14.9% 的改善.
並列摘要
In the normal physical layout migration solution, both physical design rule and scaling factor are used to compact the original physical design to the target physical design. This method also affects the MOS transistor width. Although this method can produce the migration result 100% DRC correct, but the timing issues are not concerned during the physical layout migration process. In this thesis, an optimization solution for physical layout migration had been provided by integrating the Perl scripts, into commercial EDA tools design flow. The result from the physical layout migration can have better timing result than the traditional physical migration method. This methodology first analyzing the SPICE model of target process and original physical design, then using the physical layout migration tool to achieve a timing optimized layout. In the experimental result, the physical layout migration result of this methodology can have 14.9% improvement in the timing than the traditional one.