以可規劃系統晶片設計為基礎之快速向量量化器碼字搜尋演算法則積體電路設計

VLSI Circuit Design of Fast Codeword Search Algorithm for Vector Quantization Based on System On Programmable Chip Design

李世璋(Shih-Chang Li)

指導教授 ： 黃文吉

中原大學/工學院/電機工程研究所/碩士(2004年)

https://doi.org/10.6840/cycu200400624

摘要

向量量化器編碼端中，最費時的部份就是碼字搜尋，碼字搜尋包含大量的加減法、乘法以及邏輯判斷等運算，在軟體計算中，這些將會造成很高的計算複雜度，因此將花費大量的碼字搜尋時間。
本論文提出了一個以可規劃系統晶片(System On Programmable Chip, SOPC)設計為基礎的快速向量量化器碼字搜尋法則之硬體架構，適用於以向量量化器為基礎之影像編碼應用。此架構將一個具有向量量化器碼字搜尋運算加速功能之專用硬體電路與 Nios 嵌入式處理器系統整合在一可規劃系統晶片中，以達到系統之高效能與積體化。
本論文所提出之專用硬體電路架構結合了小波轉換與部分距離碼字搜尋法(PDS)，包含Haar 離散小波轉換運算單元、量化誤差計算單元、部分距離搜尋單元、碼簿唯讀記憶體以及控制單元。另外提出一適用於多個模組之平行運算架構，在同於單一模組的搜尋精確度之下達到更高速的計算。
我們使用 Altera SOPC 設計流程實現本論文所提出之架構於Cyclone EP1C20F400C7 Device，並於 Nios 平台完成系統驗證及效能比較。由比較結果可以發現本論文所提之架構有優於Pentium Ⅲ 1GHz以及Pentium IV 2.4 GHz微處理器的運算效能。

關鍵字

可規劃系統晶片 ； 部分距離碼字搜尋 ； Nios 嵌入式處理器

並列摘要

To the encoder of vector quantizer, the most time-consuming part is codeword search. Codeword search includes a large amount of addition, subtraction, multiplication and logic operation. These will cause very high calculation complexity when calculated in the software. It will spend a large number of time for codeword search.
In this thesis, we present a hardware architecture of fast codeword search algorithm based on SOPC(System On Programmable Chip) design, suitable for image encoding application based on vector quantization. This architecture integrates one specialized hardware circuit includes operational accelerating function of vector quantizer codeword search and Nios Embedded Processor System into one programmable chip. It is with high efficiency and integrated for the system.
The specialized hardware architecture that this thesis put forward has combined the Wavelet Transform and Partial Distance Search(PDS), includes the Haar DWT Unit, Distortion Calculation Unit, PDS Unit, Codebook ROM and Control Unit. We present a parallel processing architecture suitable for multi-modules in addition, and this reach more high-speed calculation under the accuracy of searching same as the single module.
We use Altera SOPC design flow to implement the architecture of this thesis we present in the Cyclone EP1C20F400C7 device, and complete system verification and efficiency comparison in Nios platform. We can find that the operation efficiency of the architecture we present is superior to Pentium Ⅲ 1GHz and Pentium IV 2.4GHz microprocessor by the comparative result.

並列關鍵字

System On Programmable Chip ； Nios Embedded Processor ； Partial Distance search

參考文獻

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