以切割法為基礎之電壓降導向元件擺置方法

隨著製程技術的進步，伴隨而產生的問題也越來越多，電源網路上所產生的電壓降效應（IR Drop）就是其中一種，電壓降效應會使得電路時序延長，造成電路的時序以及功能錯誤，尤其當製程技術進入深次微米以後，電壓降現象越來越嚴重，因此如何能夠減少最大電壓降值是一個重要的課題。本篇論文呈現一個以切割法為基礎最佳化最大電壓降的元件擺置方法，我們於元件擺置階段除了考量晶片的總線長外，同時也考量標準元件的排列與電壓降效應的關係，將功率消耗大的元件往row的中央搬動，功率消耗小的元件往row的兩端搬動，減少了晶片電壓降值，當元件擺置結束後，我們從電壓降最嚴重的row上搬動標準元件至其他的row，減少晶片上最嚴重的電壓降值。相對於WL-Driven Placement，本演算法能夠減少44％之最大電壓降值。藉由我們提出的元件擺置方法，除了可以於元件擺置階段估計電壓降值並且降低電壓降效應，也可以減少利用Power Straps降低電壓降效應的需求，降低空間成本。

關鍵字

電壓降；元件擺置

並列摘要

As the process technology progress, signal integrity problem becomes an important issue. One of them is the IR drop problem. IR drop reduces voltage on a chip, and increases the delay of the circuits. When the IR drop becomes excessive, the functions of the circuits may be failed. IR drop becomes more critical in deep submicron designs. Therefore, how to reduce the maximum IR drop value has become an important issue. In this study, a partition-based IR drop-driven standard cell placement algorithm is proposed. We consider the location of the standard cells relative to the power source to reduce the IR drop value during placement. After that, we consider the total wire length of the chip and move standard cells from the row with maximum IR drop value to a new location such that the maximum IR drop is reduced. Placement generated by the proposed approach is compared with the WL-Driven placement. On average, the proposed approach improves the maximum IR drop value by 44%. Besides, it can reduce the need of adding the power straps on the chip by using our approach.

並列關鍵字

IR Drop ； Placement

參考文獻

[1] Joon-Seo Yim; Seong-Ok Bae; Chong-Min Kyung;, "A floorplan-based planning methodology for power and clock distribution in ASICs [CMOS technology]", Design Automation Conference, 1999. Proceedings. 36th , 21-25 June 1999

[2] Bai, G.; Bobba, S.; Hajj, I.N., "Simulation and optimization of the power distribution network in VLSI circuits",Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on , 5-9 Nov. 2000

[3] Dae Woon Kang; Yong-Bin Kim;, "Design flow of robust routed power distribution for low power ASIC", Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on , Volume: 1 , 26-29 May 2002

[6] Zarkesh-Ha, P.; Meindl, J.D.;,” Optimum on-chip power distribution networks for gigascale integration (GSI)”, Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International, 4-6 June 2001

[8] Graziano, M.; Masera, G.; Piccinini, G.; Zamboni, M.;,” Automated power supply noise reduction via optimized distributed capacitors insertion” , Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on , 25-27 Feb. 2001

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以切割法為基礎之電壓降導向元件擺置方法

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